Abstract: An electric motor drive unit includes a winding switching unit that switches a configuration of windings of an electric motor, a winding switching instruction unit that generates an instruction signal for the winding switching unit, and a winding configuration retention unit to which the instruction signal generated by the winding switching instruction unit is input, and if the input instruction signal has a first value, outputs a signal corresponding to the input instruction signal to the winding switching unit, and if the input instruction signal has a second value different from the first value, continues outputting a signal that has been output to the winding switching unit before the reception of the second value, the first value indicating an instruction on the configuration of the windings.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: This disclosure describes a method for shorting one or more windings in a steering motor. The method determines that a signal has not been received at a circuit from a processor. The method discharges a first capacitor in the circuit in response to the circuit not receiving the signal from the processor. The method turns on a first plurality of transistors via a resistor in response to discharging the first capacitor. The method turns on a second plurality of transistors in response to turning on the first plurality of transistors. The method sends a short circuit signal from the second plurality of transistors to a steering motor.

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

Abstract: An inverter device includes: an inverter, a power supply current detection sensor, a phase current detection sensor, a three-phase voltage command calculator, and an inverter on/off signal generation unit. The phase current detection sensor detects a phase current in one phase of the inverter. The inverter on/off signal generation unit generates on/off signals based on the phase voltage commands. The three-phase voltage command calculator uses the power supply current and the phase current detected by the power supply current detection sensor and the phase current detection sensor, respectively, so as to calculate phase voltage commands directed to the inverter, and at a center time point of a period in which an upper arm switching element corresponding to one phase out of two phases for which the phase current detection sensor is not provided is on, and lower arm switching elements corresponding to the other two phases are on.

Abstract: Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.

Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k(k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Abstract: A method for manufacturing a chip card is provided by electroconductive connecting of a chip module to a chip-card body having at least one electrical contact area. The method includes adhesively connecting the chip module to the chip-card body by a thermoplastic, electroconductive elastomeric material such that the chip module is conductively connected to at least one electrical contact area of the chip-card body.

Abstract: A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.

Abstract: A component carrier with a) a first component carrier portion having a blind opening; b) a component arranged in the blind opening; and c) a second component carrier portion at least partially filling the blind opening. At least one of the first component carrier portion and the second component carrier portion includes a flexible component carrier material, and the first component carrier portion and the second component carrier portion form a stack of a plurality of electrically insulating layer structures and/or electrically conductive layer structures. It is further described a method for manufacturing such a component carrier.

Abstract: An all-electronic high-throughput detection system can perform multiple detections of one or more analyte in parallel. The detection system is modular, and can be easily integrated with existing microtiter plate technologies, automated test equipments and lab workflows (e.g., sample handling/distribution systems). The detection system includes multiple sensing modules that can perform separate analyte detection. A sensing module includes a platform configured to couple to a sample well. The sensing module also includes a sensor coupled to the platform. The sensing module further includes a first electrode coupled to the platform. The first electrode is configured to electrically connect with the sensor via a feedback circuit. The feedback circuit is configured to provide a feedback signal via the first electrode to a sample received in the sample well, the feedback signal based on a potential of the received sample detected via a second electrode.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

Abstract: The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state.

Abstract: A multilayer substrate includes a stacked body including first and second flexible insulating base material layers, and an actuator conductor pattern on at least the first insulating base material layer. The stacked body includes a first region including stacked first and second insulating base material layers, and a second region including stacked second insulating base material layers. The first region includes an actuator function portion in a portion thereof, the actuator function portion including the actuator conductor pattern. The thickness of the first insulating base material layer including the actuator conductor pattern is smaller than the thickness of one second insulating base material layer.

Abstract: The present disclosure relates to a device that includes an active layer and a first charge transport layer, where the first charge transport layer includes a first layer and a second layer, the first layer is in contact with the second layer, the second layer is positioned between the first layer and the active layer, the first layer comprises a first carbon nanostructure, and the second layer includes a second carbon nanostructure.

Abstract: A controller apparatus for an electric power tool is provided where the electric power tool includes a battery and a DC brushless motor. The controller apparatus includes a current detector that detects an instantaneous current flowing in the DC brushless motor; a current calculator that calculates one of an average value and an effective value of the instantaneous current detected by the current detector; a current controller configured to utilize a result from the current calculator as a detected value; and a speed controller configured to generate a target value of the current controller. The controller apparatus further includes a limiter that limits the target value of the current controller, where the limiter is provided at an output stage of the speed controller.

Abstract: Provided are a printed circuit board in which warps are effectively suppressed, and a semiconductor package having a semiconductor device mounted on said printed circuit board, even though circuit patterns of different amounts of metal are formed on both sides of one cured product of a prepreg. Specifically, said printed circuit board is a printed circuit board which comprises a cured product of a prepreg comprising a fiber base material and a resin composition, in which circuit patterns of different amounts of metal are formed on both sides of one cured product of the prepreg, in which said prepreg has layers on the front and back of said fiber base material, wherein said layers comprise resin compositions having different heat curing shrinkage rates, in which among these layers, the layer made of the resin composition having a smaller heat curing shrinkage rate is present on the side on which the circuit pattern with a smaller amount of metal is formed.

Abstract: An AC-AC power convertor converts a first AC voltage to a second AC voltage. A PFC rectifier circuit rectifies an AC voltage (vG) so as to generate a rectified voltage. An inverter generates the second AC voltage from the rectified voltage. A controller controls the PFC rectifier circuit and the inverter such that power generated by the first AC voltage and the pulsations of power generated by the rectified voltage are output to an external device.

Abstract: A sensorless position estimation and control system and method for a permanent magnet electric motor of a powertrain system of a vehicle involve determining a reference torque to be achieved by the electric motor based on a set of vehicle operating parameters, determining a reference current magnitude to achieve the determined reference torque using a lookup table, determining current commands for the electric motor based on the determined reference current magnitude and a fixed reference current angle, injecting a high frequency voltage into a voltage control loop for the electric motor and estimating, by the controller, a position of a rotor of the electric motor thereafter, and controlling a current provided to the electric motor based on the determined current commands and the estimated rotor position.

Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively.