Patents Examined by T. N. Quach
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Patent number: 7355276Abstract: A circuit assembly for mounting one or more integrated circuits that effectively dissipates heat generated by the integrated circuits, and a corresponding method for fabricating such a circuit assembly. The circuit assembly comprises a substrate, a thermally-conductive adhesive layer and a heat-dissipating layer. The substrate includes an opening extending between a first surface and a second surface of the substrate. An integrated circuit is to be mounted on the first surface of the substrate substantially coincident with the opening. The thermally-conductive adhesive layer is at least partially disposed within the opening in the substrate. The heat-dissipating layer is disposed on the second surface of the substrate and includes a raised portion that at least partially extends through the opening in the substrate.Type: GrantFiled: March 10, 2006Date of Patent: April 8, 2008Assignee: Maxtor CorporationInventors: Mark R. Lanciault, Mark R. Dunbar, Stanislaw Dobosz
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Patent number: 7355234Abstract: A stacked capacitor formed in a capacitor hole includes a bottom electrode, capacitor insulation film and a top electrode. The bottom electrode includes a plurality of islands formed on an underlying insulating film, and a metallic film covering the islands on the underlying insulating film. The larger surface of the bottom electrode increases the capacitance of the stacked capacitor.Type: GrantFiled: January 4, 2006Date of Patent: April 8, 2008Assignee: Elpida Memory, Inc.Inventor: Akira Hoshino
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Patent number: 7355277Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.Type: GrantFiled: December 31, 2003Date of Patent: April 8, 2008Assignee: Intel CorporationInventors: Alan M. Myers, R. Scott List, Gilroy J. Vandentop
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Patent number: 7348613Abstract: The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.Type: GrantFiled: March 14, 2005Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 7339215Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.Type: GrantFiled: February 13, 2007Date of Patent: March 4, 2008Assignee: Texas Instruments IncorporatedInventor: PR Chidambaram
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Patent number: 7339229Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.Type: GrantFiled: June 16, 2006Date of Patent: March 4, 2008Assignee: Chingis Technology CorporationInventors: Alex Wang, Shang-De Ted Chang, Han-Chih Lin, Tzeng-Huei Shiau, I-Sheng Liu, Hsien-Wen Liu
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Patent number: 7339236Abstract: The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n? type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.Type: GrantFiled: February 13, 2006Date of Patent: March 4, 2008Assignee: Renesas Technology Corp.Inventors: Tetsuya Nitta, Yasunori Yamashita, Shinichiro Yanagi, Fumitoshi Yamamoto
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Patent number: 7338862Abstract: Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region within the body layer. A recess region is formed in the floating body region. A gate electrode is formed in the recess region. Impurity ions of a first conductivity type are implanted into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.Type: GrantFiled: January 19, 2006Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Zong-Liang Huo, Seung-Jae Baik, In-Seok Yeo, Hong-Sik Yoon, Shi-Eun Kim
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Patent number: 7339223Abstract: Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.Type: GrantFiled: June 6, 2006Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hoo-Ouk Lee, Hyo-Dong Ban
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Patent number: 7339232Abstract: A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.Type: GrantFiled: October 21, 2005Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Young Seo, Hee-Seog Jeon, Sung-Taeg Kang
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Patent number: 7335532Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.Type: GrantFiled: November 17, 2006Date of Patent: February 26, 2008Assignee: Fairchild Semiconductor CorporationInventors: Jonathan A. Noquil, Seung Yong Choi, Rajeev Joshi, Chung-Lin Wu
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Patent number: 7335543Abstract: A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlying the surface region. A gate polysilicon layer is overlying the gate dielectric layer. A mask layer is overlying the gate polysilicon layer. The device also has a gate electrode formed within the gate polysilicon layer. The gate electrode has a first predetermined width and a first predetermined thickness. Preferably, the gate electrode has a first side and a second side formed between the first predetermined width. The gate electrode is coupled to the double diffused drain region within the well region.Type: GrantFiled: August 27, 2004Date of Patent: February 26, 2008Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: John Chen, Roger Lee
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Patent number: 7329914Abstract: A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.Type: GrantFiled: July 1, 2004Date of Patent: February 12, 2008Assignee: Macronix International Co., Ltd.Inventor: Yen-Hao Shih
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Patent number: 7326952Abstract: An elevated phase-change memory cell facilitates manufacture of phase-change memories by physically separating the fabrication of the phase-change memory components from the rest of the semiconductor substrate. In one embodiment, a contact in the substrate may be electrically coupled to a cup-shaped conductor filled with an insulator. The conductor couples current up to the elevated pore while the insulator thermally and electrically isolates the pore.Type: GrantFiled: May 5, 2004Date of Patent: February 5, 2008Assignee: Ovonyx, Inc.Inventor: Tyler A. Lowrey
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Patent number: 7323749Abstract: A semiconductor device with a plurality of passive components (7,7a,8,8a) comprising a bottom substrate (1), a buried oxide layer (2) on a portion of the top surface of the bottom substrate (1), an dielectric intermediate insulating layer (3) on a portion of the buried oxide layer (2), a dielectric top insulating layer (4), and at least one implanted passive component (7a,8a) of a semiconductor material implanted under the buried oxide layer (2) within the top surface portion of the bottom substrate (1), the implanted semiconductor material having a material polarity being opposite to the bottom substrate polarity. When the implanted passive component (7a) is an AC decoupling capacitor (7a), the bottom and side portions of the implanted semiconductor material are surrounded by a depletion layer (7b) of a semiconductor material implanted between said bottom substrate (1) and said implanted semiconductor material.Type: GrantFiled: February 14, 2006Date of Patent: January 29, 2008Assignee: Seiko Epson CorporationInventor: Kazuaki Tanaka
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Patent number: 7323783Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.Type: GrantFiled: December 6, 2004Date of Patent: January 29, 2008Assignee: NEC CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
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Patent number: 7321147Abstract: A device including a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor is provided. The device also includes a cell transistor including diffused regions formed in a surface of a semiconductor substrate; a trench capacitor formed in said semiconductor substrate for configuring a DRAM cell together with said cell transistor; a buried strap formed in said semiconductor substrate to connect said diffused region to said trench capacitor; and a collar insulation film formed on sides of said buried strap.Type: GrantFiled: January 17, 2006Date of Patent: January 22, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Mutsumi Okajima
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Patent number: 7320910Abstract: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.Type: GrantFiled: November 20, 2006Date of Patent: January 22, 2008Assignee: Renesas Technology Corp.Inventor: Motoi Ashida
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Patent number: 7319252Abstract: Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends between a first end and an opposing second end, each of the first and second ends being affixed to the substrate. Other embodiments are described and claimed.Type: GrantFiled: June 28, 2004Date of Patent: January 15, 2008Assignee: Intel CorporationInventor: Peter L. D. Chang
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Patent number: 7315057Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.Type: GrantFiled: March 3, 2006Date of Patent: January 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hee Seog Jeon, Sung-Taeg Kang, Hyok-Ki Kwon, Yong Tae Kim, BoYoung Seo, Seung Beom Yoon, Jeong-Uk Han