Abstract: An error rate measuring apparatus includes a demodulator, and data from the demodulator is applied to a decoding circuit in which an error bit number is evaluated for each of a BIC portion and a packet portion. In the BIC portion, if a synchronization is settled, the error bit number is evaluated by comparing received BICs and a predetermined BIC pattern, and if the synchronization is not settled, the error bit number is determined as eight (8) bits. In the packet portion, if a frame synchronization is settled and decoding is successful, the error bit number is calculated by comparing data before decoding and data after decoding with each other. If the frame synchronization is settled but the decoding is unsuccessful, a presumed error bit number is set according to the number of packets being decoded successfully in a first time horizontal direction, and if the frame synchronization is not settled, a predetermined error bit number is set.

Abstract: A transmission equipment comprising a center management device collecting data from units connected to subscriber terminals. The center management device includes two processing units and a control unit for controlling operational states of the first and second processing unit in such a way that when one of the two processing units is working, the other of the two processing units is in a standby state. The two processing units process the same data by using a data backup unit whereby all of the units can be made by hardware which may be easily replaced or added. Alternatively, each unit may have a program downloading unit so that if a new function is added or new unit is added, the program in the unit may be down loaded to the center management device.

Abstract: A data integrity system comprising a plurality of units connected together for the transfer of data between the units. Each said unit comprises data means for receiving data from one or more other units and/or transmitting data to one or more other units, first means, if the unit transmits data to other units, for generating a PARITY OUT signal indicating the parity of all data transmitted to the other units and second means, if the unit is to receive data from other units, for generating a PARITY IN signal indicating the parity of all data being received by the unit from the other units. A third means, located in one of said plurality of units, receives all the PARITY OUT signals and all the PARITY IN signals generated by the plurality of units and detects from all the received PARITY IN signals and all the PARITY OUT signals whether an error had occurred during the transfer of data between the units.

Abstract: Data is stored in and read from a semiconductor memory system including multiple memory integrated circuits in data units commonly exchanged with a rotating memory device. One or more data units to be stored are clustered with a multiplicity of other data units stored in the semi conductor memory to form a cluster of data units. The cluster of data units is compressed, and the compressed cluster of data units is then error correction coded. The compressed cluster of data units is then stored in the semiconductor memory with a multiplicity of contiguous data bits being stored in a single memory integrated circuit. Data compression reduces the number of memory integrated circuits required, thereby reducing both cost and power consumption. Data is stored in and read out of the memory integrated circuits serially such that only a single memory integrated circuit is active at a time, further reducing power consumption.

Abstract: A parity circuit generates an output parity bit responsive to a plurality of data input bits. The parity circuit comprises a plurality of transistor stages coupled to the input bits and the output bit, the value of the input bits defining at least one charging path through the transistor stages. The charging path is coupled at first and second nodes to a power supply, such that the charging path is supplied with current at both ends, thereby increasing the responsiveness of the parity circuit.

Abstract: A fault-tolerant computer system has primary and backup computers. Primary and backup virtual machines running on the computers are controlled by corresponding virtual machine monitors. The virtual machines execute only user-mode instructions, while all kernel-mode instructions are trapped and handled by the virtual machine monitors. Each computer has a recovery register that generates a hardware interrupt each time that a specified number of instructions, called an epoch, are executed. Prior to failure of the primary computer, the backup computer's virtual machine monitor converts all I/O instructions into no-ops and the primary computer sends copies of all I/O interrupts to the backup computer.

Abstract: An asynchronous transfer mode (ATM) cross-connect unit is used in an ATM communication system which includes at least two communication stations which may be coupled via a plurality of ATM cross-connect units.

Abstract: A method and accompanying apparatus for identifying a system, such as illustratively a central processing unit (CPU), that holds a "reserve" for a shared physical device (480, 482, 484) employed within illustratively a multi-processing environment. Specifically, sense data (500) returned by execution of a Reset Allegiance (R/A) command, by a control unit of a shared device, contains the path group identifier (PGID) (300) for a path group (680) through which a reserve has been extended. Inasmuch as the PGID is created in an identical manner for all operating systems (VM or MVS) that share devices through an MVS operating system (600), the PGID advantageously and uniquely specifies the CPU then holding this reserve. The PGID contained in the returned sense data is then translated, through a table look-up operation, in illustratively a so-called IOS Record (1100) situated in a Coupled Dataset (620) for a sysplex installation (455), to yield a common system name of the particular CPU then holding the reserve.

Abstract: A portable computer including a CPU, a detachable hard disk pack which is connectable to a system bus of the portable computer, and a hard disk pack replacement detector which detects, in a power-OFF state, a detachment of the disk pack and sets a signal in a status register indicating the detachment of the disk pack. In response to a power-ON state, the CPU reads the status register to determine whether the disk pack had been detached during the power-OFF state and, if so, disables a resume flag so that operation does not resume at the operating state of the portable computer which existed immediately preceding the power-OFF state.

Abstract: A fault clearance and recovery operation in an electronic reprographic system comprises storing in memory clearance and recovery instructions for specific system faults, monitoring the system for fault occurrence and accessing displaying the stored instructions upon detection of a fault occurrence. Faults having similar recovery features are classified into buckets to facilitate the clearance and recovery operations.

Abstract: Stations on a faulty token ring which includes a control adapter are removed one at a time starting with the most down stream station from the control adapter or of a station up stream from the last station is known to be good all of the stations down stream from that station are removed and the one at a time removal starts with the known good station. The control adapter transmits special beacon frames during the station removal process and when the removal of a station results in receipt of the special beacon frame at the control adapter, the control program identifies a fault domain which includes the station whose removal caused the special beacon to be received at the control adapter and the station immediately up stream from that station. The stations in the fault domain are selectively subjected tests and removed from the ring when a failure is detected.

Abstract: An array processing circuit which operates on a M row-N column array of digital words includes a first set of N memories, each of which asynchronously receives a respective column of words from a separate input channel; and, a second set of N memories which have respective inputs that are coupled to corresponding outputs of the first set of memories. A first addressing circuit detects when each memory of the first set contains a respective word of the same row, and in response transfers that row of words in parallel to the second set of memories. N-1 column error detect circuits respectively detect when a column of words from the first N-1 memories of the first set has an error.

Abstract: A method of and apparatus for continuously checking a CMOS SRAM memory system. Each memory cell has a bistable circuit for retaining the state of the cell, along with a totally redundant bistable circuit. Added circuitry provides continuous comparing of the binary state of the bistable circuit and the redundant bistable circuit within the memory cell. This testing is performed at a low level within the memory cell eliminating the power dissipation and size requirements associated with additional drivers. An error line is shared amongst a number of memory cells. By continuously monitoring in this manner, the time of failure as well as the fact of failure can be determined.

Abstract: A computer boot strap loading system employs dual, separable EEPROM units to facilitate safe reprogramming of bootstrap loader software. Both EEPROMs are adapted for storing bootstrap loading code. One of these two EEPROM areas is designated as the unit for which the code content will govern operation of the next reboot sequence. Circuitry is provided to monitor progress of a reboot to determine if a defect in the presently utilized reboot sequence is provided. Such a defect triggers a reboot from the other EEPROM as well as to provide a back-up copy of the bootstrap loading code most recently determined to be effective.

Abstract: An improved cross-checking circuit is provided for use within a Reed-Solomon error correction and cross checking apparatus for performing error correction and cross checking upon a data block within an incoming stream of substantially contiguous data blocks flowing from a source to a destination. The circuit is based upon a distinguished primitive element, alpha.sup.1 (2B (Hex))=x.sup.5 +x.sup.3 +x+1, of a Galois field whose elements are represented by residue classes of binary polynomials modulo p(x)=x.sup.8 +x.sup.4 +x.sup.3 +x.sup.2 +1. The apparatus includes a microcontroller for supervising the flow of the data blocks and for making calculations related to error corrections, and a Galois field syndrome generator and remainder recovery circuit is connected to receive the incoming stream and recover therefrom plural error correction remainder bytes for each block and selectively to hold said bytes in a syndrome latch, the remainder bytes being related to syndrome bytes appended to the data block.

Abstract: A signal period detection circuit detects the period of clock signals and generates a control signal for computer memory. The control signal is used in conjunction with an alternate refresh circuit that provides alternate refresh control signals to DRAM when the computer is not properly operating. When the clock period varies from normal operating parameters, the control signal is sent to the alternate refresh circuit to supply continuous refresh and power signals to the DRAM.

Abstract: An apparatus for distinguishing a wanted signal in a binary signal sequence having both wanted signals and interference signals includes the step of generating a correction value which has a first value to indicate a wanted binary signal and a second value to indicate a binary interference signal. The wanted signal has a preselected maximum number of bits. A first counter counts the bits of the binary signal sequence and changes the correction value from the first value to the second value when the preselected maximum is exceeded. The correction value is reset to the first value when the temporal spacing between two occurrences of excesses of the preselected maximum number exceeds a predetermined spacing.

Abstract: A facility is provided for improving the quality of data that is stored in a data base. Such improved quality is achieved by tracking the operation of various processes controlling respective data processors, which assemble/modify a data record that is ultimately stored in the data base such that random ones of the data records are marked prior to supplying them to a first one of the processors and then obtaining from each of the processors a copy of a marked data record that it processes. Copies of respective data records are then analyzed to determine which of the processes may be corrected to improve the quality of the data that is stored in the data base.

Abstract: In order for a disk control unit with built-in cache to write non-reflective data in the cache to a disk drive without stopping extension of a read/write command from host computer in the event of a fault in the cache or its backup memory, the track data in normal one of the cache and its backup memory is written to a certain physical track of the disk drive upon judging at read/write command execution that the accessed track is a non-reflective track, and a read/write command from the host computer is implemented for the physical track of the disk drive which has completed the non-reflective track write operation.

Abstract: An automatic skew calibration technique for a multi-channel signal source uses a cross-coupled flip-flop calibration circuit and a microprocessor to align the timing of a pair of signals from the multi-channel signal source. The flip-flop calibration circuit indicates which of the pair of signals is leading, and the microprocessor uses the output of the flip-flop calibration circuit to determine in which signal source to adjust the signal delay. The signal source is incrementally delayed by the microprocessor while the microprocessor also observes the output of the flip-flop calibration circuit. When the flip-flop calibration circuit indicates a time interval over which the relative time position of the input signals changes, then the microprocessor determines a calibrated value for the signal delay, completing skew calibration of the multi-channel signal source.