Abstract: Disclosed are a decoding method and a decoding device. In the method, a received sequence and a generator matrix are processed to obtain a hard-decision information sequence and a hard-decision codeword; an error pattern is determined according to the hard-decision information sequence and the hard-decision codeword; then, the error pattern is post-processed and an optimal decoding sequence is output as a decoding result, wherein the optimal decoding sequence is a decoding sequence with a minimized Euclidean distance. According to the present disclosure, the complexity of the algorithm is reduced while the effective decoding performance can be ensured.

Abstract: A semiconductor memory device includes; a memory semiconductor die including a volatile memory device configured to perform a normal operation in response to at least one of a command and an address received from a host device, and a test chip vertically stacked with the memory semiconductor die and including a nonvolatile memory device. The test chip is configured in the normal mode to store log information corresponding to at least one of a command and an address received by the semiconductor memory device from the host device, and is further configured in a debugging mode to read the log information from the nonvolatile memory device.

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than 4G communication systems such as LTE systems. The disclosure relates to a method and device for dynamically selecting, or simultaneously performing, PAC code-based Fano decoding and/or list decoding in a wireless communication system. The method for performing PAC code-based decoding by a reception device in a wireless communication system comprises identifying a specific criterion variable related to a channel state for selecting at least one of Fano decoding or list decoding for a signal received from a transmission device, comparing the specific criterion variable related to the channel state with a threshold, performing the Fano decoding in case that the specific criterion variable related to the channel state satisfies the threshold, and performing the list decoding in case that the specific criterion variable related to the channel state does not satisfy the threshold.

Abstract: A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.

Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

Abstract: Methods and systems are disclosed for sending a first parameter of a plurality of parameters to a third dedicated address of a plurality of addresses in memory, updating a parameter flag value in a first dedicated address in memory, updating a cyclic redundancy check (CRC) value for the parameter flag in a second dedicated address in memory, writing a first parameter value for the first parameter in the third dedicated address and updating the CRC value of the first parameter to a fourth dedicated address in memory, sending a second parameter to a fifth dedicated address of the plurality of addresses in memory, writing a second parameter value for the second parameter in the fifth dedicated address and updating the CRC value of the second parameter in a sixth dedicated address, and identifying a monitoring result between read values and expected values.

Abstract: A data processing method, an apparatus, and a device are disclosed. The data processing method may be performed by a first communications device, and the first communications device is a transmit end of encoded data. The first communications device may send a high-order signal to a second communications device by using a plurality of parallel channels, and information bits in the parallel channels are arranged in a specified order. The method helps improve a transmission rate in a parallel channel transmission scenario, and helps the second communications device perform correct decoding.

Abstract: A terminal according to one embodiment of the present invention determines and reports a specific codebook-based HARQ-ACK on the basis of the result of receiving a plurality of PDSCHs, and, on the basis of a first-type codebook-based HARQ-ACK having been set for scheduling of the plurality of PDSCHs, the terminal can perform first start symbol and length indicator value (SLIV) pruning on the basis of a set of the SLIVs of PDSCHs, which can be potentially scheduled on each slot of a bundling window determined on the basis of a plurality of candidate PDSCH-to-HARQ feedback timing values, and perform second SLIV pruning on the basis of a set of the SLIVs of PDSCHs, which can be potentially scheduled even on at least one slot that does not belong to the bundling window.

Abstract: A semiconductor integrated circuit includes a write test circuit and a read test circuit. The write test circuit generates test data and transmits the generated test data to an external memory device without storing the test data in a local memory device. The read test circuit receives from the external memory device, read data that the external memory device has obtained by reading the test data, and compares the received read data with an expected value without storing either the read data or the expected value in the local memory device.

Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

Abstract: A memory device and a control method for the memory device are provided. When it is determined that a bit read from a memory cell in a memory cell array is an erroneous bit, the memory device triggers a second reading cycle. During the second reading cycle, if the bit read from the same memory cell is still an erroneous bit, the memory cell is deemed to be a real defective memory cell. At this time, a repairing memory cell is selected from a repairing memory cell array to replace the real defective memory cell. The selected repairing memory cell and the real defective memory cell are coupled to the same word line.

Abstract: A method of operating a device in a wireless network comprising transmitting a first uplink signal comprising control information in a set of uplink resources, transmitting a second uplink signal, wherein the second uplink signal is to be transmitted a plurality of times, each of the plurality of transmissions of the second uplink signal being a repetition of the second uplink signal, wherein each repetition of the second uplink signal is to be transmitted in a different set of uplink resources to the other repetitions of the second uplink signal, determining that the resources of the first uplink signal at least partially overlap in time with the resources of at least one of the repetitions of the second uplink signal, multiplexing the control information into the resources of a selected one or more of the repetitions of the second uplink signal, and transmitting the multiplexed signal to the wireless network.

Abstract: This application provides data transmission methods, devices, and systems. In one implementation, a method comprises: receiving, by a central device of a wireless network, at least one first data packet sent by a remote device of the wireless network, wherein each of the at least one first data packet comprises a sequence number indicating a relative location of a payload of the corresponding first data packet in a second data packet; reordering, by the central device, the at least one first data packet, based on the sequence number of each of the at least one first data packet, to obtain the second data packet; and sending, by the central device, the second data packet.

Abstract: A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.

Abstract: A detection system for a SlimSAS slot and a method thereof are disclosed. In the detection system, a detecting device generates and transmits a detection signal to a TAP controller; the TAP controller converts the received detection signal into a detection signal in JTAG format, and transmits the detection signal in JTAG format to a CPLD chip and a controllable power module chip of a detection card and/or a boundary scan chip of a circuit board; a detection can be performed on the SMBus pins, the differential signal receiving pins, the differential signal transmitting pins, the clock pins, the sideband pins and the ground pins of the SlimSAS connection interface through the boundary scan chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip. Therefore, the technical effect of improving slot stability and detection coverage of a SlimSAS slot detection can be achieved.

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

Abstract: This disclosure introduces an advancement to the error indication message to provide detailed information about errors in configurations that are arriving from the Layer 2 to the Layer 1. A method is disclosed, comprising: performing physical layer control (PHY) of a wireless signal at a Layer 1 (L1) software module; performing medium access control (MAC) of the wireless signal at a Layer 2 (L2) software module; providing an application programming interface between the L1 software module and the L2 software module for receiving L1 configuration messages and providing error codes to the L2 software module; receiving a L1 configuration message at a Layer 1 software module; and providing an enhanced error code progressively from a L1 software module to the Layer 2 (L2) software module.