Patents Examined by T. Tu
  • Patent number: 11907560
    Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 11892508
    Abstract: A joint test action group transmission system includes a host terminal and a slave terminal. The slave terminal includes a test access port (TAP) circuit, an internal memory, and a memory interface controller. The TAP circuit includes a test data register set. The memory interface controller stores the data received from the TAP circuit to the internal memory. The host terminal transmits a set of download instruction bits to the TAP circuit to have the TAP circuit select the test data register set, and have the TAP circuit enter a data shift status to receive a data package through the test data register set. During the process of receiving the data package, the TAP circuit remains in the data shift status to receive the address and at least one piece of data stored in the data package continuously.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 6, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chen-Tung Lin, Yuefeng Chen
  • Patent number: 11892907
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: February 6, 2024
    Assignee: Kioxia Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 11892504
    Abstract: Systems and methods of debugging a design under test for metastability issues using formal verification. In one aspect, the method includes determining, by a server, that a functionality of the DUT failed an assertion; generating, by the server, a plurality of first waveforms for a plurality of clock domain crossing (CDC) pairs that are in a cone of influence of the assertion; applying, by the server, a constraint including a condition to the plurality of waveforms; and generating, by the server, one or more second waveforms for a first subset of the plurality of CDC pairs, wherein the first subset of the CDC pairs satisfied the condition.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: February 6, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alberto Arias Drake, Bijitendra Mittra, Keyliane da Silva Fernandes Silvano
  • Patent number: 11894091
    Abstract: A system, program product, and method for processing synchronized memory repairs. The method includes identifying a faulty memory row from a plurality of functioning memory rows in a memory array. The method also includes executing memory row repair operations directed toward the faulty memory row and identifying a repair row to operationally replace the faulty memory row. The method also includes creating a multiple hot state within a memory decoder. The memory decoder includes logic circuitry for executing operation of the plurality of functioning memory rows. The method further includes activating a wordline of the identified repair row through the multiple hot state, and executing one or more memory operations on the identified repair row though the memory decoder. Accordingly, the embodiments disclosed herein facilitate synchronization of the repair row and functioning memory rows within the memory array, as well as any associated peripheral signals.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 6, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yaron Freiman, Noam Jungmann, Tomer Abraham Cohen, Elazar Kachir, Hezi Shalom
  • Patent number: 11881275
    Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Adolfo Cano, Devanathan Varadarajan, Anthony Martin Hill
  • Patent number: 11880277
    Abstract: Selecting an error correction code type for a memory device includes: selecting, by the memory device in dependence upon predefined selection criteria, one of a plurality of error correction code types and carrying out memory access requests utilizing the selected error correction code type.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 23, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sudhanva Gurumurthi, Vilas Sridharan
  • Patent number: 11876533
    Abstract: In a method for computer-assisted operation of a memory unit, encoded data is saved in the memory unit. The data is retrieved and decoded after retrieval. The memory unit is monitored for errors in that a temporal sequence of computer-assisted checking operations is carried out for the memory unit. For first-time encoding of the data, each required application data set is generated or selected, containing check data segments. For each application data set, the check data segment is occupied by count data, which characterizes the checking operation being implemented. After retrieving and decoding the application data sets, an error is determined when the count data characterizes neither the checking operation being implemented nor the most recent completely implemented checking operation. The check data segment of the relevant application data set is occupied by count data, which characterizes the checking operation being implemented, if no error was determined.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: January 16, 2024
    Assignee: Siemens Mobility GmbH
    Inventors: Andreas Schallenberg, Markus Seemann, Stefan Gerken
  • Patent number: 11860731
    Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: January 2, 2024
    Inventors: Martin Brox, Peter Mayer, Wolfgang Anton Spirkl, Thomas Hein, Michael Dieter Richter, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11853158
    Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: December 26, 2023
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 11853599
    Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Takeshi Nakano, Akihiko Ishihara, Shingo Tanimoto, Yasuaki Nakazato, Shinji Maeda, Minoru Uchida, Kenji Sakaue, Koichi Inoue, Yosuke Kino, Takumi Sasaki, Mikio Takasugi, Kouji Saitou, Hironori Nagai, Shinya Takeda, Akihito Touhata, Masaru Ogawa, Akira Aoki
  • Patent number: 11854637
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, David G. Springberg
  • Patent number: 11842786
    Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 12, 2023
    Assignee: APPLE INC.
    Inventors: Nir Tishbi, Ilia Benkovitch, Ruby Mizrahi
  • Patent number: 11836041
    Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: December 5, 2023
    Inventors: Chulseung Lee, Soon Suk Hwang, Choongeui Lee
  • Patent number: 11835578
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: December 5, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11838124
    Abstract: A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Ho Myung, Kyung-Joong Kim, Hong-Sil Jeong
  • Patent number: 11837313
    Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta, Chulmin Jung
  • Patent number: 11829237
    Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: November 28, 2023
    Assignee: Apple Inc.
    Inventors: Marc A Schaub, Roy G. Moss, Michael Bekerman
  • Patent number: 11817170
    Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes outputting a first command including a request for on-chip valley search (OVS) count data of a memory region of the non-volatile memory device to the non-volatile memory device, wherein the OVS count data include a first count value of a first read voltage and a second count value of a second read voltage, receiving the OVS count data from the non-volatile memory device, determining a first error count value for the first read voltage and a second error count value for the second read voltage, based on the OVS count data, and determining a subsequent operation, based on the first and second error count values.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: November 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woohyun Kang, Youngdeok Seo, Hyuna Kim, Hyunkyo Oh, Heewon Lee, Donghoo Lim
  • Patent number: 11810634
    Abstract: Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Sadayuki Okuma