Patents Examined by T. Tu
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Patent number: 11153036Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.Type: GrantFiled: June 15, 2020Date of Patent: October 19, 2021Assignee: Panasonic Intellectual Property Corporation of AmericaInventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
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Patent number: 11145386Abstract: A chip testing method, device, electronic apparatus, and computer readable medium are provided, relating to the field of chip testing. The method includes: determining a language rule of a chip to be tested; determining product and timing specifications of the chip to be tested; selecting a test pattern from a test pattern library according to the language rule and the product and timing specifications; generating a test code according to the product and timing specifications and the test pattern; and automatically testing the chip to be tested by using the test code. The chip testing method, device, electronic apparatus and computer readable medium can automatically generate a big-data test code for complex memories, and rapidly generate, in a standardized way, test codes for DDR4 memories of different specifications, thereby improving the efficiency of chip product verification analysis.Type: GrantFiled: February 16, 2021Date of Patent: October 12, 2021Assignee: Changxin Memory Technologies, Inc.Inventor: Ruei-Yuan Guo
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Patent number: 11137446Abstract: A test apparatus is configured to test a DUT that does not support synchronous control from an external circuit. A main controller is configured based on an architecture that tests a device by synchronous control with the main controller itself as the master. A MIU is configured as an interface between the main controller and the DUT. The MIU establishes asynchronous control between it and the DUT with the DUT as the master, and establishes control between it and the main controller with the main controller as the master.Type: GrantFiled: September 24, 2019Date of Patent: October 5, 2021Assignee: ADVANTEST CORPORATIONInventors: Shuichi Inage, Kazuhiro Iezumi, Tomoyuki Itakura, Keisuke Kusunoki, Yoshihiro Kato, Kazuhiro Tsujikawa, Naoya Kimura, Yuki Watanabe, Yuichiro Harada, Koji Miyauchi
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Patent number: 11125816Abstract: A method is used to test a memory device including a package substrate, a controller die and a memory die. The package substrate includes an isolation pin, a test mode select pin, a test clock pin and a test data pin. The method includes setting the isolation pin to an isolation state to isolate the memory die from the controller die, and when the isolation pin is set to the isolation state, setting the memory die to receive control via the test mode select pin, the test clock pin and the test data pin.Type: GrantFiled: December 23, 2019Date of Patent: September 21, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Xiaodong Xu, Xiangming Zhao, Shunlin Liu, Yi Chen
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Patent number: 11113145Abstract: A memory device includes a plurality of pages. Each page includes a data region configured to store data, an error correction code (ECC) region configured to store ECC data that is used to detect and correct one or more errors occurring in the data stored in the data region, and a metadata region configured to store a write count of a corresponding page.Type: GrantFiled: February 19, 2019Date of Patent: September 7, 2021Assignee: SK hynix Inc.Inventor: Chang Hyun Park
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Patent number: 11106532Abstract: A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.Type: GrantFiled: April 29, 2020Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
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Patent number: 11094394Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.Type: GrantFiled: September 24, 2019Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
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Patent number: 11088712Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.Type: GrantFiled: November 5, 2019Date of Patent: August 10, 2021Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, David Avraham, Eran Sharon
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Patent number: 11088711Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.Type: GrantFiled: July 8, 2019Date of Patent: August 10, 2021Assignee: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
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Patent number: 11068340Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.Type: GrantFiled: February 17, 2020Date of Patent: July 20, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sanguhn Cha, Hoyoung Song, Myungkyu Lee, Sunghye Cho
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Patent number: 11055164Abstract: There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.Type: GrantFiled: November 6, 2019Date of Patent: July 6, 2021Assignee: SK hynix Inc.Inventors: Soon Young Kang, Dae Sung Kim, Wan Je Sung, Myung Jin Jo, Jae Young Han
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Patent number: 11050437Abstract: Parity logic is widely used in forward error correction codes and error detection codes. When used for error correction and error detection applications, the role of parity bits is to increase code distance by introducing memory between encoded bits and input bits at cost of overhead bits. Present disclosure provide systems and methods for implementing invertible parity functions using parity logic wherein ‘k’ input bits are received and encoded using a first invertible parity function. The ‘k’ input bits can be iteratively encoded to obtain nonlinearity and higher dependency between set of encoded parity bits and the ‘k’ input bits or other data bits. Further the decoding is performed on the set of encoded bits to retrieve original ‘k’ input bits using a second invertible parity function.Type: GrantFiled: June 26, 2020Date of Patent: June 29, 2021Inventor: Mahesh Rameshbhai Patel
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Patent number: 11048580Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.Type: GrantFiled: February 20, 2020Date of Patent: June 29, 2021Assignee: MICRON TECHNOLOGY, INC.Inventors: Samuel E. Bradshaw, Justin Eno, Sean Stephen Eilert, Sai Krishna Mylavarapu
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Patent number: 11042437Abstract: A computer-implemented method, according to one embodiment, includes: receiving, at a storage drive, a portion of a write command. Metadata information is extracted from the received portion of the write command, and sequentially added to a metadata buffer. Parity information is extracted from the received portion of the write command, and adding to a parity buffer. The data in the received portion of the write command is stored in a memory in the storage drive. A determination is also made as to whether an open segment in the memory which corresponds to the received portion of the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. The metadata information and parity information is also destaged from the respective buffers to a physical storage location in the memory.Type: GrantFiled: July 10, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
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Patent number: 11042436Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.Type: GrantFiled: August 29, 2019Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Aaron Jannusch, Brett K. Dodds, Debra M. Bell, Joshua E. Alzheimer, Scott E. Smith
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Patent number: 11042432Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.Type: GrantFiled: December 20, 2019Date of Patent: June 22, 2021Assignee: Western Digital Technologies, Inc.Inventors: Abhijit Rao, Ramanathan Muthiah, Judah Gamliel Hahn, Gautam Ashok Dusija, Daniel Linnen
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Patent number: 11036399Abstract: A memory system may include: a plurality of memory devices each including a user area and an over-provisioning area (OP area); and a controller configured for controlling the plurality of memory devices, wherein the controller includes: a detection circuit configured for detecting a defective memory device among the plurality of memory devices; a selection circuit configured for selecting an available memory device excluding the defective memory device among the plurality of memory devices; and a processor configured for moving target data stored in the defective memory device into the OP area of the available memory device.Type: GrantFiled: March 13, 2019Date of Patent: June 15, 2021Assignee: SK hynix Inc.Inventor: Sun-Woong Kim
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Patent number: 11036580Abstract: A computer-implemented method, according to one embodiment, includes: sequentially adding metadata information that has been extracted from a received write command to a metadata buffer, and adding parity information that has been extracted from the received write command to a parity buffer. The data corresponding to the received write command is also sent to memory. A determination is made as to whether an open segment in the memory which corresponds to the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. Moreover, the metadata information is destaged from the metadata buffer and parity information is destaged from the parity buffer to a physical storage location in the memory.Type: GrantFiled: July 10, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
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Patent number: 11038530Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).Type: GrantFiled: July 19, 2019Date of Patent: June 15, 2021Assignee: WESTHOLD CORPORATIONInventors: Shu Lin, Khaled Ahmed Sabry Abdel-Ghaffar, Juane Li, Keke Liu
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Patent number: 11016843Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.Type: GrantFiled: December 6, 2018Date of Patent: May 25, 2021Assignee: Micron Technology, Inc.Inventor: Kiyoshi Nakai