Patents Examined by T. Tu
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Patent number: 11569844Abstract: A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability.Type: GrantFiled: June 24, 2020Date of Patent: January 31, 2023Assignee: Western Digital Technologies, Inc.Inventors: Shay Benisty, Ran Zamir, Eran Sharon
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Patent number: 11567828Abstract: A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.Type: GrantFiled: July 9, 2020Date of Patent: January 31, 2023Assignee: SK hynix Inc.Inventors: Fan Zhang, Aman Bhatia
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Patent number: 11568951Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.Type: GrantFiled: March 12, 2020Date of Patent: January 31, 2023Assignee: Texas Instruments IncorporatedInventors: Francisco Adolfo Cano, Devanathan Varadarajan, Anthony Martin Hill
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Patent number: 11557370Abstract: A semiconductor device includes an external terminal, an input buffer having an input terminal connected to the external terminal, a voltage generating circuit configured to generate a test voltage supplied to the input terminal, and a control circuit configured to determine whether the input buffer is deteriorated based on the test voltage supplied to the input terminal and an output level of the input buffer responding to the test voltage.Type: GrantFiled: April 9, 2021Date of Patent: January 17, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke Katagiri, Terunori Kubo, Hirotsugu Nakamura
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Patent number: 11550650Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.Type: GrantFiled: December 9, 2019Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventor: Dean D. Gans
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Patent number: 11543452Abstract: A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.Type: GrantFiled: September 8, 2020Date of Patent: January 3, 2023Assignee: XILINX, INC.Inventors: Saikat Bandyopadhyay, Rajvinder S. Klair, Dhiraj Kumar Prasad, Ender Tunc Eroglu, Rupendra Bakoliya, Jayashree Rangarajan
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Patent number: 11538549Abstract: A test circuit includes a control circuit and a counting circuit. The control circuit is configured to control a charging operation and a discharging operation on a test node. The counting circuit is configured to generate counting information by performing a counting operation during a unit measurement interval.Type: GrantFiled: January 28, 2021Date of Patent: December 27, 2022Assignee: SK hynix Inc.Inventors: Jong Seok Jung, Sung Won Choi
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Patent number: 11537465Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.Type: GrantFiled: February 12, 2021Date of Patent: December 27, 2022Assignee: KIOXIA CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
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Patent number: 11531063Abstract: According to one embodiment, a design support device executes a first processing. The first processing includes setting a control value group for a semiconductor element. The semiconductor element includes gates including first and second gates. The control value group includes a first time difference between first and second timings. A voltage is applied to the first gate at the first timing. A voltage is applied to the second gate at the second timing. The first processing includes calculating a characteristic value from an output result when an electrical signal corresponding to the control value group is input to the semiconductor element. The first processing includes calculating a first function from history data including not less than one data set. The data set includes the control value group and a score based on the characteristic value. The design support device sets a new control value group.Type: GrantFiled: August 25, 2021Date of Patent: December 20, 2022Assignee: Kabushiki Kaisha ToshibaInventor: Tatsunori Sakano
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Patent number: 11520513Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.Type: GrantFiled: October 20, 2020Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11521696Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.Type: GrantFiled: October 22, 2020Date of Patent: December 6, 2022Assignee: SK hynix Inc.Inventors: Young Jun Park, Young Jun Ku, Myeong Jae Park, Ji Hwan Park, Seok Woo Choi
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Patent number: 11514994Abstract: A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit of the flash controller. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.Type: GrantFiled: October 21, 2021Date of Patent: November 29, 2022Assignee: Microchip Technology Inc.Inventors: Lorenzo Zuolo, Rino Micheloni
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Patent number: 11514971Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.Type: GrantFiled: April 30, 2021Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kihwan Seong, Soomin Lee, Sanghune Park
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Patent number: 11509333Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.Type: GrantFiled: December 17, 2020Date of Patent: November 22, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Shrikanth Ganapathy, John Kalamatianos
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Patent number: 11509418Abstract: Disclosed in an embodiment of the present invention are a polar code encoding method and device, the method comprising: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead.Type: GrantFiled: April 2, 2021Date of Patent: November 22, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Hui Shen, Bin Li, Jun Chen
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Patent number: 11495315Abstract: A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.Type: GrantFiled: August 11, 2021Date of Patent: November 8, 2022Assignee: Siemens Industry Software Inc.Inventors: Wei Zou, Benoit Nadeau-Dostie
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Patent number: 11494256Abstract: An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.Type: GrantFiled: June 6, 2019Date of Patent: November 8, 2022Assignee: Arm LimitedInventors: Milosch Meriac, Emre Özer, Xabier Iturbe, Balaji Venu, Shidhartha Das
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Patent number: 11489620Abstract: Identifying, by a sender and for each frame i of a plurality of frames of a video stream, a partition of a set of video data symbols D[i] into a first set of video data symbols U[i] and a second set of video data symbols V[i]. Generating, by the sender and for each frame i, a set of one or more streaming forward error correction (FEC) code parity symbols P[i] based on the symbols: V[i??] through V[i?1], U[i??], and the symbols D[i], wherein ? is a function of a maximum tolerable latency of the video stream expressed as a whole number of frames. Encoding, by the sender and for each frame i, packets carrying the symbols D[i], and P[i]. Transmitting, by the sender, each frame i of encoded packets in frame order to one or more receivers.Type: GrantFiled: September 21, 2021Date of Patent: November 1, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Ganesh Ananthanarayanan, Yu Yan, Martin Ellis, Michael Harrison Rudow
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Patent number: 11488679Abstract: Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.Type: GrantFiled: September 14, 2021Date of Patent: November 1, 2022Assignee: TEAM GROUP INC.Inventors: Hsi-Lin Kuo, Ming-Hsun Chung, Chin-Feng Chang
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Patent number: 11489621Abstract: A current frame in a sequence is encoded at a first bitrate to generate one or more encoded source frames. One or more previous frames in the sequence are encoded at a second bitrate that is lower than the first bitrate to generate one or more encoded FEC frames. The one or more encoded source frames and the one or more encoded FEC frames are packetized into one or more data packets.Type: GrantFiled: April 12, 2021Date of Patent: November 1, 2022Assignee: SONY INTERACTIVE ENTERTAINMENT LLCInventors: Kim-Huei Low, Kelvin Yong