Patents Examined by Tammara Peyton
  • Patent number: 10061726
    Abstract: A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a link delay management request on an upstream-facing port of the retimer. The method further includes receiving, at a downstream-facing port of the retimer, a link delay management request and responding to the request received on the downstream-facing port.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: August 28, 2018
    Assignee: INTEL CORPORATION
    Inventors: Steven B. McGowan, Huimin Chen
  • Patent number: 10042799
    Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 7, 2018
    Assignee: BITMICRO, LLC
    Inventors: Cyrill C. Ponce, Marizonne O. Fuentes, Gianico G. Noble
  • Patent number: 10042786
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 7, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 10034617
    Abstract: A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 31, 2018
    Assignee: BRAEMAR MANUFACTURING, LLC
    Inventors: Erich Vlach, Charles Gropper
  • Patent number: 10031868
    Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Christopher P. Mozak, James A. McCall, Bryan K. Casper
  • Patent number: 10022491
    Abstract: A medical system includes an input assembly for receiving one or more user inputs. The input assembly includes at least one slider assembly for providing an input signal. Processing logic receives the input signal from the input assembly and provides a first output signal and a second output signal. A display assembly is configured to receive, at least in part, the first output signal from the processing logic and render information viewable by the user. The second output signal is provided to one or more medical system components. The information rendered on the display assembly may be manipulatable by the user and at least a portion of the information rendered may be magnified.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 17, 2018
    Assignee: DEKA PRODUCTS LIMITED PARTNERSHIP
    Inventors: Kevin L. Grant, Douglas J. Young, Matthew C. Harris
  • Patent number: 10002088
    Abstract: Aspects of the present disclosure describe automatically changing an output mode of an output device from a first output mode to a latency reduction mode. An initiation signal and the output data may be received from a client device platform or a signal distributor. Upon receiving the initiation signal, the output device may change the output mode from the first output mode to the latency reduction mode. Thereafter, the output device may receive an end latency reduction mode signal. The output device may then revert back to the first output mode. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 19, 2018
    Assignee: Sony Interactive Entertainment LLC
    Inventor: Roelof Roderick Colenbrander
  • Patent number: 10001953
    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Leena K. Puthiyedath, Blaise Fanning, Toby Opferman, James B. Crossland
  • Patent number: 9990325
    Abstract: Embodiments relate a universal serial bus (USB) filter hub. An aspect includes receiving, by the USB filter hub that is in communication with a host computer system, a connection from a USB device at a USB port of the USB filter hub. Another aspect includes determining, by the USB filter hub, a type of the USB device. Another aspect includes determining whether the type of the USB device is valid. Yet another aspect includes, based on determining that the type of the USB device is valid, filtering commands that are communicated between the USB device and the host computer system via the USB filter hub based on a predetermined command set corresponding to the determined type of the USB device.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 5, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Hetzler, Daniel F. Smith
  • Patent number: 9984019
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hee Yoo, Jae Geun Yun, Bub Chul Jeong, Dong Soo Kang, Kyeo Rae Lee, Seong Min Jo
  • Patent number: 9977648
    Abstract: According to one embodiment, a media system communicates with an aggregate device that includes multiple media output devices. When providing media data for presentation, the system adjusts for device clock drift by resampling the media data provided to a media output device based at least in part on a device clock rate difference between a device clock of one of the media output devices and a device clock of another of the media output devices.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 22, 2018
    Assignee: Apple Inc.
    Inventors: Jeffrey C. Moore, William George Stewart, Gerhard Lengeling
  • Patent number: 9959593
    Abstract: An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 1, 2018
    Assignee: ATI Technologies ULC
    Inventors: Milivoje Aleksic, Raymond M. Li, Danny H. M. Cheng, Carl K. Mizuyabu, Anthony Asaro
  • Patent number: 9959241
    Abstract: An accessory device architecture is described. In one or more implementations, data is received from an accessory device at an integrated circuit of a computing device, the data usable to enumerate functionality of the accessory device for operation as part of a computing device that includes the integrated circuit. The data is passed by the integrated circuit to an operating system executed on processor of the computing device to enumerate the functionality of the accessory device as part of the integrated circuit.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 1, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Sharon Drasnin
  • Patent number: 9952986
    Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Akshay G. Pethe, David J. Harriman, Mahesh Wagh, Abdul Hawk Ismail
  • Patent number: 9952957
    Abstract: A method for dynamically modifying a characteristic for an electronic device. The method includes activating by a processor a first profile having a first characteristic setting and a first state for an input/output (IO) device. Once the first profile is activated, receiving an input by a sensor and communicating the input to the processor. The method then includes activating by the processor a second profile having a second characteristic setting and a second state for the IO device. The second profile modifies a component of the IO device to include a second characteristic setting and a second state.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 24, 2018
    Assignee: Apple Inc.
    Inventors: Christopher T. Mullens, Jesse Michael Devine, Marco Sebastiani, Nima Parivar
  • Patent number: 9934160
    Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 3, 2018
    Assignee: BiTMICRO LLC
    Inventors: Cyrill C. Ponce, Marizonne Operio Fuentes, Gianico Geonzon Noble
  • Patent number: 9934046
    Abstract: A method for dynamically modifying a mobile device. The method includes a computer processor identifying a plurality of profiles on a mobile device. The method further includes a computer processor receiving one or more inputs on the mobile device. The method further includes a computer processor identifying at least one trigger that corresponds to the received one or more inputs, wherein the at least one trigger is associated with at least one profile of the plurality of profiles. The method further includes a computer processor determining if the at least one trigger activates a response, based at least in part, on data included in the at least one profile that is associated with the at least one trigger. The method further includes a computer processor responding to the determination that the at least one trigger activates a response and applying the response to the mobile device.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rajaram B. Krishnamurthy, Daniel A. Rogers
  • Patent number: 9935407
    Abstract: An intelligent connector module assembly is disclosed. The intelligent connector module assembly has a master control module, at least one first execution component, and an intelligent connector module. The intelligent connector module has a communication and control unit connected to and configured to receive a control signal from the master control module, and a first switch array and drive unit connected to the communication and control unit and to the at least one first execution component. The first switch array and drive unit controls operation of the first execution component in response to the control signal received by the communication and control unit.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: April 3, 2018
    Assignee: Tyco Electronics (Shanghai) Co. Ltd.
    Inventors: Mingjie Fan, Yuming Song, Yulin Feng, Feng Dai
  • Patent number: 9928697
    Abstract: A Point-of-Sale (POS) terminal in a retail environment is communicatively connected to one or more POS peripheral devices. Each POS peripheral device is associated with a configuration file that defines configuration settings for the POS peripheral device and environmental context information for the POS terminal and the POS controller. The configuration files are prioritized according to various criteria, and used to re-configure POS applications executing on the POS to operate optimally with the particular POS peripheral device. Additionally, the prioritized configuration files control the POS applications to update the configuration information.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 27, 2018
    Assignee: Toshiba Global Commerce Solutions Holdings Corporation
    Inventors: Tong Yu, Yongan Wang, Xianhua Liu, Shaobo Dou
  • Patent number: 9916274
    Abstract: An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: March 13, 2018
    Assignee: Cavium, Inc.
    Inventors: Weihuang Wang, Dan Tu, Guy Hutchison, Prasanna Vetrivel