Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

Abstract: A network device includes Power-over-Ethernet PoE ports to communicate with a communication network and Universal Serial Bus (USB) devices. The network device establishes an Internet Protocol (IP) related connection with an application program, and receives downlink IP packets carrying USB transaction requests destined for the USB device from the application program over the IP connection. The network device converts the received downlink IP packets carrying the USB transaction requests to downlink bus-level USB transactions that are understandable to the USB device. The network device sends the downlink bus-level USB transactions to the USB adaptor device over a PoE connection for forwarding by the USB adaptor device to the USB device.

Abstract: A system for communication with a field device, comprising: an apparatus which includes a communication module and an adapter. The communication module includes a connection region and a communication area. The communication area includes at least one communication interface for communication for the field device. A first connecting structure is provided on the connection region, and a second connecting structure provided on an adapter, wherein the second connecting structure is embodied complementary to the first connecting. The adapter includes an interface, and the adapter is embodied passively A display/servicing device, wherein the interface is embodied for connection to the display/servicing device, wherein the display/servicing device is embodied as a portable mobile device, wherein the mobile device is embodied for single-use battery- or rechargeable battery operation, and wherein the first connecting, the second connecting structure and the interface are embodied as plug contacts.

Abstract: A data processing system comprising a plurality of data inputs and of data outputs for processing input data and providing processed data to a data output. The system comprises a plurality of data processing hardware units, each being configured to process data within a predetermined latency and according to a data processing task of a predetermined type. The system further comprises a memory for storing a predetermined latency for each of the data processing hardware units and a controller configured to determine a type of a data processing task to be executed as a function of a source of data to be processed or of a destination of processed data and further configured to select one data processing hardware unit as a function of the determined type of the task to be executed and of latency constraints associated with the task to be executed.

Abstract: Systems and methods for managing input/output operations of a first computing system at a second computing system are disclosed. One method includes receiving an input/output control block at a distributed input/output processor separate from a first computing system, the input/output control block built by the first computing system in response to initiation of an input/output operation at the first computing system. The method also includes enqueueing an input/output operation at the distributed input/output processor, and processing, by the distributed input/output processor, the input/output operation from memory of the first computing system. The method includes returning results from the distributed input/output processor to the first computing system.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: A switching apparatus to adapt an interface for multi-functional use includes a signal source, a display unit, a control unit, and a connector. The signal source includes a first power output and a data output. The display unit includes a power input and a data input. The control unit includes a switching chip having a control signal input, a first data pin, a second data pin, and a third data pin. The connector includes a second power input, a second power output, and a data output. The control signal input receives a switching signal. When the second data pin communicates with the first data pin according to the switching signal, the first power output is electrically coupled to the second power input, the signal source provides power for an electronic device connected with the connector.

Abstract: According to a storage system, method, and apparatus for processing an operation request provided by embodiments of the present invention, a controller directly encapsulates a SCSI protocol operation request into an Ethernet operation request packet at the MAC layer instead of using the TCP/IP protocol layer and a disk enclosure decapsulates the Ethernet operation request to obtain the SCSI protocol operation request and sends the SCSI protocol operation request to a target disk, thereby reducing layers of encapsulation, reducing a processing delay of the storage system, and improving performance of the storage system.

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: Various embodiments (“systems”) are described for transferring data from a primary storage (e.g., magnetic disk drives, solid state drives, etc.) to an optical cold storage rack. The optical cold storage rack may include many physical optical storage disks, but a much smaller number of burners and readers (e.g., optical disk drives). When data is to be transferred to the optical cold storage rack, the system may generate a plan for performing the transfer. “Migration worker” components may then implement the plan and may be exclusively dedicated to implementing such plans. In various embodiments, the plan may specify how large data file “aggregates” (collections of portions of one or more data files) are to be distributed across optical disks (“disks”) to improve throughput during subsequent reading operations from the optical cold storage rack. The plan may also anticipate the relation between the limited number of burners/readers and the overall optical cold storage rack disk capacity.

Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract: A method includes executing a data processing application including a static part for performing at least the following functions: determining at least one identifier of an exercise monitoring device which is connected to the computing device, wherein the connected exercise monitoring device comprises exercise-related data; indicating the determined at least one identifier to a first server over a network, wherein the first server stores operational attributes for a plurality of different exercise monitoring devices; and receiving information indicating operational attributes associated with the connected exercise monitoring device from the first server, wherein the indicated operational attributes form an exercise monitoring device-specific dynamic part of the data processing application. The method also includes performing, by the dynamic part, at least one operation to the exercise-related data on the basis of the indicated operational attributes associated with the connected exercise monitoring device.

Abstract: The invention relates to a input/output device transferring and/or receiving data to and/or from a control device, wherein the input/output device transfers the data to the control device over a physical connection of the Ethernet type according to a UDP/IP protocol, the input/output device being connected to a plurality of data processing or acquisition devices by means of at least one connection different from the Ethernet physical connection and in that the input/output device includes means for connecting at least one other input/output device to the Ethernet connection and for managing the transmission over the Ethernet connection of the data transmitted by the input/output devices to the control device.

Abstract: An embodiment of the disclosure relates to the field of data transmission, in particular to a data transmission method and a data transmission device, for solving the problems of low data transmission efficiency and poor Direct Memory Access (DMA) performance in a method of arbitrating each DMA channel in a round-robin mode and transmitting data according to an arbitration result. The method in the embodiment of the disclosure includes that: for each DMA channel, an arbitration unit corresponding to the channel among a plurality of arbitration units is determined according to transmission performance corresponding to data in the channel; and when data in channels corresponding to at least two arbitration units need to be transmitted, the data are transmitted according to priorities of the at least two arbitration units.

Abstract: One or more examples provide techniques to dynamically manage serial port interface(s) of virtualization software executing in a host device. In an example, a method of managing a serial port interface of a virtualization software executing on a host device includes: receiving input characters through the serial port interface to a serial port of the host device; parsing the input characters to detect a character sequence; and connecting the serial port interface to a first service executing in the virtualization software in response to the character sequence and during execution of the virtualization software on the host device.

Abstract: A relaying device, when having received an interrupt notification 151 from an I/O device, transmits an interrupt factor read request 159(1) for an interrupt factor to the I/O device, based on an address information memory table 1041, without waiting for a response from a CPU, and transmits the interrupt notification 151 received, to the CPU. When having received an interrupt factor 160(1), the relaying device transmits an intra-I/O-device data read request 159(2) to the I/O device, based on an intra-I/O-device data read address storing table 1081, without waiting for a response from the CPU.

Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Abstract: Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request.