Abstract: Polychoric correlations between two discrete random variables and polyserial correlations between a discrete random variable and a continuous random variable may be determined by using a normal-to-anything (NORTA) method and a stochastic root finding algorithm.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Abstract: Methods and apparatus disclosed herein operate, for example, to derive a non-ideal received signal from an ideal signal, to compute, from the non-ideal received signal, at least one probability density function of amplitude and time values representing deviations from the ideal signal, to derive at least one amplitude noise component and at least one timing jitter component from the at least one probability density function, and to generate a non-ideal waveform by applying the at least one amplitude noise component and the at least one timing jitter component to an ideal waveform.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

Abstract: A high-speed continuous-time FIR (finite impulse response) filter comprises a plurality of processing cells configured in a cascade topology. Each processing cell receives a first signal and a second signal from a preceding circuit and a succeeding circuit, respectively, and outputs a third signal and a fourth signal to the succeeding circuit and the preceding circuit, respectively. Each processing cell further comprises a delay cell and a summing cell. Each of the delay cell and the summing cell performs a high speed signal processing using a combination of a feedback loop and a feedforward path.

Abstract: A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (13), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder (11c) for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.

Abstract: Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Abstract: A signal processing apparatus includes a first filter on an in-phase signal channel; a second filter on a quadrature signal channel; a plurality of filter stages having each of more than one signal paths crossing each other which connects the first filter and the second filter; and at least more than one of the filter stages of more than one of a plurality of the filter stages includes a switching circuit disconnecting more than one of the signal paths and a correction unit correcting direct current offsets of the first filter and the second filter by using the switching circuit.

Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

Abstract: An Inverse Hadamard Transform (IHT) converter and system includes a first group of registers for receiving coefficients inputted to the IHT converter; a first adder for adding selected the coefficients stored in the first group of registers; a second group of registers for receiving results from the first adder; and a second adder for adding selected the results stored in the second group of registers.

Abstract: Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers x, y, z are generated such that x?Rx, y?Ry, z?Rz, and z=round ( x op y). Solutions are provided for add and subtract operations. Range constraints are imposed on the input operands and on the result operand of floating point add and subtract instructions to target corner cases when generating test cases for use in verification of floating point hardware.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: A system having a pseudo random number generator, a control circuit being configured to increase a quality of a pseudo random number output signal of the pseudo random number generator by coupling the pseudo random number generator with a true random number output signal of a true random number generator and a consumer circuit being configured to use the pseudo random number output signal before and after the increase.

Abstract: Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences.

Abstract: An apparatus for processing a plurality of real-valued subband signals using a first real-valued subband signal and a second real-valued subband signal to provide at least a complex-valued subband signal comprises a multiband filter for providing an intermediate real-valued subband signal and a calculator for providing the complex-valued subband signal by combining a real-valued subband signal from the plurality of real-valued subband signals and the intermediate subband signal.

Abstract: An apparatus for processing a plurality of real-valued subband signals using a first real-valued subband signal and a second real-valued subband signal to provide at least a complex-valued subband signal comprises a multiband filter for providing an intermediate real-valued subband signal and a calculator for providing the complex-valued subband signal by combining a real-valued subband signal from the plurality of real-valued subband signals and the intermediate subband signal.

Abstract: A first representation of an electrical network includes a first set of simultaneous linear algebraic equations (SLAE's). A second representation of an electrical network includes a second set of SLAE's. The equations of the SLAE's include a number of unknowns and have coefficients for the respective unknowns. A number of the coefficients are expressed in algebraic form. The coefficients of one such equation from one of the sets of SLAE's are for respective elements of the set's respective electrical network and the unknowns are for respective operating properties of the set's respective electrical network. Results are derived in pairs for each unknown of each respective one of the SLAE's. The pairs of results are compared in a specified manner to determine a network equivalence. The results are derived from the SLAE's and expressed in algebraic form, so that the comparing of the pairs of results includes comparing algebraic expressions.

Abstract: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.