Abstract: A filter controller. In one embodiment, the filter controller includes a first mechanism for providing an input signal to an adjustable filter. A second mechanism measures a response of the adjustable filter to the input signal and provides a second signal in response thereto. A third mechanism sets one or more parameters of the adjustable filter in response to the second signal. In a more specific embodiment, the adjustable filter includes one or more sub-filters, such as a canceller filter, which may be any filter that employs one or more portions or versions of a signal to selectively cancel one or more portions or versions, such as frequency components, of the same signal.

Abstract: Techniques are presented for randomly generating bits. A seed is inverted and a non repeating portion of the resulting digits from the inversion are retained. The inverted seed is then raised to a power to acquire another non repeating portion or additional digits. This process is repeated for a desired number of iterations. The resulting digits are then selectively combined to generate a stream of randomly generated bits with an infinite period.

Abstract: A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.

Abstract: There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.