Abstract: A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction.

Abstract: A method for depositing nanowires is disclosed. The method includes depositing multiple nanowires onto a surface of a liquid. The method also includes partially compressing the nanowires. The method also includes dipping a substrate into the liquid. The method further includes pulling the substrate out of the liquid at a controlled speed. The method also includes transferring the nanowires onto the substrate parallel to a direction of the pulling.

Abstract: A light-emitting diode includes a substrate (12) having an upper surface, a lower surface, and a peripheral side surface, a pair of upper electrodes (13a, 13b) provided on upper surface portions of the substrate, at least one light emitting element (14) mounted one of the pair of upper electrodes, and a covering member (18) provided on the upper surface of the substrate except the upper surface portions at which the pair of upper electrodes are provided. The covering member (18) includes a recess (19), and a light-shielding resin (20) filled in the recess (19).

Abstract: A backside-illuminated imaging device, which performs imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light and reading out the electric charges from a front side of the semiconductor substrate, is provided and includes: a back-side layer including an back-side element on the back side of the semiconductor substrate; a front-side layer including an front-side element on the front side of the semiconductor substrate; a support substrate above the front-side layer; a spacer, one end of which comes in contact with the front-side layer and the other end of which comes in contact with the support substrate, to form a space having a uniform distance between the semiconductor substrate and the support substrate; and an adhesive filled in at least a part of the space between the surface-side element formation layer and the support substrate.

Abstract: An electrooptical device having a plurality of light-emitting regions includes a substrate, a bank disposed in a region other than the light-emitting regions on the substrate so as to surround the light-emitting regions, and a functional layer disposed in openings surrounded by the bank. The bank includes an upper bank segment and a plurality of lower bank segments having a higher wettability than the upper bank segment. The number of the lower bank segments exposed is smaller in second regions of the openings than in first regions of the openings.

Abstract: A method for fabricating a crown-shaped capacitor includes providing a first dielectric layer with a protective pillar formed thereover, including a first conductive layer, a protective layer, and a mask layer. A second conductive layer is formed over a sidewall of the protective pillar. A first capacitance layer and a third conductive layer are formed over the first dielectric layer. A sacrificial layer is formed over the third conductive layer. The sacrificial layer, the third conductive layer, the first capacitance layer, the second conductive layer, and the mask layer above the protective layer are partially removed. The second conductive layer and the third conductive are removed to form a recess adjacent to the first capacitance layer. The protective layer is removed and an opening is formed to expose the first and second conductive layers. A second capacitance layer and a fourth conductive layer are formed in the opening. The sacrificial layer is removed to expose the third conductive layer.

Abstract: A MRAM structure is disclosed that includes a metal contact bridge (MCB) which provides an electrical connection between a MTJ top electrode and an overlying bit line. The MCB has a width greater than a MTJ top electrode and serves as an etch stop during bit line etching to prevent sub-trenches from forming adjacent to the top electrode and causing shorts. MCBs also prevent insufficient etching that causes open circuits. A MCB is preferably a metal, metal compound, or alloy such as Ta with low resistivity and high conductivity. The MCB layer is patterned prior to using a dual damascene process to form a bit line contacting each MCB and a bit line pad connection to a word line pad. MCB thickness is thin enough to allow a strong bit line magnetic field for switching a free layer and large enough to function as an efficient oxide etch stop.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film.

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.

Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

Abstract: An LED having enhanced heat dissipation is disclosed. For example, an LED die can have extended bond pads that are configured to enhance heat flow from an active region of the LED to a lead frame. A heat transmissive substrate can further enhance heat flow away from the LED die. By enhancing heat dissipation, more current can be used to drive the LED. The use of more current facilitates the production of brighter LEDs.

Abstract: A memory cell includes a first electrode, a second electrode, and phase change material between the first electrode and the second electrode. The phase change material has a step-like programming characteristic. The first electrode, the second electrode, and the phase change material form a via or trench memory cell.

Abstract: An LED having enhanced heat dissipation is disclosed. For example, an LED die can have extended bond pads that are configured to enhance heat flow from an active region of the LED to a lead frame. A heat transmissive substrate can further enhance heat flow away from the LED die. By enhancing heat dissipation, more current can be used to drive the LED. The use of more current facilitates the production of brighter LEDs.

Abstract: A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: A semiconductor device is provided, which comprises a first transistor and a second transistor formed in a semiconductor layer. The first transistor includes a first source region and a first drain region sandwiching a first gate electrode with the first source region. The second transistor includes an LDD region and a drift region sandwiching the second gate electrode with the LDD region, and a second drain region adjacent to the drift region to sandwich the second gate electrode with the second source region. The first gate electrode has a first sidewall formed on sides thereof and the second gate electrode has a second sidewall formed on sides thereof. The width of the former along the first insulator differs from the width of the latter along the second insulator.

Abstract: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.