Abstract: To restore data, substantially continuous recording of input/output (I/O) operations in a storage system is performed to provide an I/O continuum of I/O operations. Based on analyzing activity associated with the storage system, points in the I/O continuum associated with valid data are identified. Data in the storage system is restored to one of the identified points.

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract: A system and method for the capture, storage and manipulation of remote information is disclosed. The system includes at least one remote information capture device located at a remote site for capturing remote data, a central database accessible by the remote capture device for storing the captured remote data, and a computer program operative to manipulate the captured data. The method includes the steps of capturing remote data, storing the captured remote data, and manipulating the stored data.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

Abstract: A method for automatically identifying an operating system for a USB device begins at initializing the USB device, and recording USB commands sent from the operating system. The USB device determines the operating system as a first operating system when there are two successive USB commands of Get Product String, there is one USB command of Get Vender String, there is no USB command of Reset ahead of a USB command of Set Address, there is no USB command of Get Language ID, or there is no USB command of Set Feature Report. The USB device determines the operating system as a second operating system when there is no USB command of Get Vender String, there are two USB commands of Get Language ID and two USB commands of Get Product String, there is one USB command of Get Device Descriptor following a USB command of Get Product String, or there is one USB command of Set Interface Report.

Abstract: In a network regulated so that the unique identification information for a basic storage apparatus and that of each of a plurality of additional storage apparatuses do not overlap, the storage apparatuses can be connected to the network without being assigned unique identification information. The basic storage apparatus judges, when an additional storage apparatus is powered-on, whether or not an initial value is set in an identification information setting unit in the additional storage apparatus, the identification information setting unit being where unique identification information in the network is set. If it is judged that an initial value is set in the identification information setting unit, the basic storage apparatus enters a first mode in which it creates unique identification information, replaces the initial value with the created identification information, and recognizes the created identification information as unique identification information in the network.

Abstract: Object data representing an image object extracted from image data is stored. A display unit displays the image object or the contour of the image object in accordance with the display mode designated by a user.

Abstract: The present invention relates to a flash memory card that is a structure using a rigid flexible board (RFB) to connect a flash memory card unit and a universal serial bus (USB) unit. A communication interface in compliance with the specification of the flash memory card is disposed at one end of the flash memory card, and a USB communication interface is disposed at another end, and a rigid flexible board is provided for connecting the electric signals between the two communication interfaces and the bending characteristic is used to maintain the height difference between the planes of the two communication interface, so that the flash memory card can concurrently have the USB communication interface and enhance the applicability of the flash memory card.

Abstract: An extension to the Universal Serial Bus (USB) protocol that utilizes reserved bits in the OHCI Endpoint Descriptors to signal which root hub port(s) should transmit the data. Typically, all ports transmit (broadcast) data. The present invention encodes transmission information that can be used by the hardware to effectively control which port(s) need to be tri-stated. However, by setting, the “on” bits for all the ports, the present invention retains standard USB functionality. Also provided is a method to increase the bandwidth of low speed devices connected to the USB bus by increasing the data payload for such devices.

Abstract: In a multimedia system, a method and system for deglitching in a mobile multimedia processor are provided. A deglitching operation may be provided to reduce noise and compensate for strobe signal delays that may result in false bus cycles and other operating errors. A circuit comprising a plurality of delay cells, a multiplexer, and a latch may be utilized to perform the deglitching operation. The delay cells may be selected from several delay options having different time delays based on operating temperature and applied supply voltage. The time delay may be programmable and may be dynamically varied in accordance with the operation of the mobile multimedia processor.

Abstract: Provided are an apparatus and a method of managing a reconfiguration data memory. A space for a memory that stores configuration data used for reconfiguration of a target system is not provided in the target system. Instead the configuration data is stored in a separate server and, if required, the configuration data is transmitted to the target system through an Internet. Data that should be preserved after the reconfiguration among data contents stored in SoC internal and external memories of the target system is transferred to the server. The emptied space of the SoC internal and external memories is used as a configuration memory. After the reconfiguration, the preservation data is returned to its original position in the memories.

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract: A system including a storage processing device with an input/output module. The input/output module has port processors to receive and transmit network traffic. The input/output module also has a switch connecting the port processors. Each port processor categorizes the network traffic as fast path network traffic or control path network traffic. The switch routes fast path network traffic from an ingress port processor to a specified egress port processor. The storage processing device also includes a control module to process the control path network traffic received from the ingress port processor. The control module routes processed control path network traffic to the switch for routing to a defined egress port processor. The control module is connected to the input/output module. The input/output module and the control module are configured to interactively support data virtualization, data migration, data journaling, and snapshotting.

Abstract: Disclosed is a structured model for developing PIO code and for performing PIO transactions. This model of structured PIO transactions provides a framework with default behaviors. Developers need only provide a minimal amount of configuration information and can then characterize subsequent PIO transactions in terms of a profile, thus reducing the amount of detailed and often redundant information that developers need to provide for each PIO transaction. In some embodiments, the PIO transaction model is expressed in terms of object-oriented programming constructs. In one example, a PIO enabler object captures general PIO operational parameters and manages underlying operating system objects and behavior. When device manager software receives an input/output request that involves a PIO data transfer, the device manager constructs a PIO transaction object that represents the PIO work request. During the processing of the PIO transaction, the PIO transaction object maintains state and status information.

Abstract: The invention relates to a data output method and to a data output system comprising: a printing device; a database device, in which corresponding reference data and/or control data are stored for a plurality of data output system users; and a data output control device that delivers, at points in time determined by the data output control device, output data sets allocated to corresponding users to the printing device, wherein a predefined subset of the output data sets is—for performing a test printing—delivered to the printing device in advance already.

Abstract: A Flash-interfaced Fingerprint Sensor is disclosed. The sensor device interfaces directly with a flash memory interface chip. The flash memory interface chip incorporates the system for interfacing with flash memory devices, a fingerprint sensor/detector system, and an encryption subsystem for encrypting data being passed to and from the flash memory devices and the host computing device. The device further employs an advanced encryption approach that entails fingerprint decryption and verification on the host computer rather than on the portable memory apparatus. Once verification at the host computer is complete, memory and host functionality is enabled.

Abstract: An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed.

Abstract: A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers. At least two consecutive data transactions are executed with respect to non-contiguous system locations.

Abstract: An apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains.