Patents Examined by Telly D Green
  • Patent number: 11411015
    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Collin Howder, Chet E. Carter
  • Patent number: 11410967
    Abstract: A display device includes a display panel including a display area and a non-display area defined therein and including a plurality of signal pads overlapping the non-display area, an electronic component including a base layer with an upper surface and a lower surface, a plurality of driving pads disposed on the lower surface of the base layer, and a plurality of driving bumps respectively disposed on the plurality of driving pads, the plurality of driving bumps being respectively connected to the signal pads, and a filler disposed between the display panel and the electronic component. A first hole is defined in the upper surface of the base layer, and the first hole does not overlap the plurality of driving bumps in a plan view.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chan-Jae Park, Kikyung Youk, Sangduk Lee, Hyun a Lee, Daehwan Jang
  • Patent number: 11410960
    Abstract: A bonding apparatus includes a bonding stage on which either a rectangular substrate or a circular substrate can be installed; a first transport mechanism which transports the rectangular substrate from a first carry-in unit to the bonding stage and from the bonding stage to a first carry-out unit; and a second transport mechanism which transports the circular substrate from a second carry-in/out unit to the bonding stage and from the bonding stage to the second carry-in/out unit, in which a first transport path determined by the first transport mechanism and a second transport path determined by the second transport mechanism partially overlap.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 9, 2022
    Assignee: SHINKAWA LTD.
    Inventors: Kohei Seyama, Tetsuya Utano
  • Patent number: 11404534
    Abstract: Some embodiments relate to a semiconductor structure including a semiconductor substrate having a frontside surface and a backside surface. An interconnect structure is disposed over the frontside surface. The interconnect structure includes a plurality of metal lines and vias that operably couple semiconductor transistor devices disposed in or on the frontside surface of the semiconductor substrate to one another. A trench is disposed in the backside surface of the semiconductor substrate. The trench is filled with an inner capacitor electrode, a capacitor dielectric layer overlying the inner capacitor electrode, and an outer capacitor electrode overlying the capacitor dielectric layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu
  • Patent number: 11398492
    Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 26, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Tianhong Yan, Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11393758
    Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Loke Yip Foo, Wai Ling Lee
  • Patent number: 11380876
    Abstract: The disclosure provides a display substrate, a method for manufacturing the same and a display device, belonging to the display technology field, to solve the problem that ultraviolet irradiation has an adverse effect on the service life of existing OLED devices. The display substrate disclosed herein includes a light processing layer which comprising a condensed-ring conjugated polymer. The light processing layer can protect the display parts below it and prevent the display parts from being exposed to ambient light and reducing their service life.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 5, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongwei Tian, Yanan Niu, Dong Li, Ming Liu, Zheng Liu, Chunyang Wang
  • Patent number: 11380538
    Abstract: A nitride film forming method includes repeating a cycle a plurality of times, wherein the cycle includes: forming a layer containing an element to be nitrided on a substrate by supplying a source gas including the element to the substrate; plasmarizing a modifying gas including a hydrogen gas, and modifying the layer containing the element with the plasmarized modifying gas; and activating a nitriding gas including nitrogen by heat, and thermally nitriding the layer containing the element with the nitriding gas activated by heat.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 5, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroki Murakami
  • Patent number: 11373963
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Patent number: 11355526
    Abstract: A display apparatus includes a substrate, a display unit, a wire structure, and a first power supply structure. The substrate includes a display area, a first non-display area neighboring the display area, a second non-display area, and a bending area between the first non-display area and the second non-display area. The display unit is on the display area. The wire structure is on the first non-display area, the bending area, and the second non-display area and includes a first wire set and a second wire set overlapping the bending area and spaced from each other. The first power supply structure includes a first conductive line and a second conductive line on the first non-display area and the second non-display area, respectively, and includes a connection line connecting the first conductive line to the second conductive line and positioned between the first wire set and the second wire set.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 7, 2022
    Inventors: Hyungjun Park, Jaewon Kim, Seungwoo Sung, Junyong An, Youngsoo Yoon, Ilgoo Youn, Jieun Lee, Yunkyeong In, Donghyeon Jang, Junyoung Jo
  • Patent number: 11355722
    Abstract: To provide a light-emitting element which uses a fluorescent material as a light-emitting substance and has higher luminous efficiency. To provide a light-emitting element which includes a mixture of a thermally activated delayed fluorescent substance and a fluorescent material. By making the emission spectrum of the thermally activated delayed fluorescent substance overlap with an absorption band on the longest wavelength side in absorption by the fluorescent material in an S1 level of the fluorescent material, energy at an S1 level of the thermally activated delayed fluorescent substance can be transferred to the S1 of the fluorescent material. Alternatively, it is also possible that the S1 of the thermally activated delayed fluorescent substance is generated from part of the energy of a T1 level of the thermally activated delayed fluorescent substance, and is transferred to the S1 of the fluorescent material.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 7, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Hiromi Seo, Tatsuyoshi Takahashi
  • Patent number: 11355565
    Abstract: The present disclosure relates to a display panel. More specifically, the display panel is configured to surround an opening area, includes a reflective electrode including an inclined surface, and therefore provides increased luminous efficiency.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 7, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: JungSun Beak, Seongjoo Lee, Sunmi Lee
  • Patent number: 11335734
    Abstract: An organic light emitting diode display device includes a substrate, first and second active patterns, and first and second sub-pixel structures. The substrate has a first sub-pixel circuit region including a first driving transistor region and a second sub-pixel circuit region including a second driving transistor region. The first active pattern is disposed in the first sub-pixel circuit region and has a first bent portion in the first driving transistor region. The second active pattern is disposed in the second sub-pixel circuit region and has a second bent portion in the second driving transistor region. In a direction in a plan surface, the first active pattern has a first recess formed by the first bent portion, and the second active pattern has a second recess formed by the second bent portion. An area of the second recess is less than that of the first recess.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 17, 2022
    Inventors: Dae-Won Lee, Tae Kon Kim
  • Patent number: 11335562
    Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bang-Tai Tang, Tai-Chun Huang
  • Patent number: 11335598
    Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Sudipto Naskar, Manish Chandhok, Miriam Reshotko, Rami Hourani
  • Patent number: 11335644
    Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo, Daniele Vimercati
  • Patent number: 11329219
    Abstract: In a method of manufacturing a magnetoresistive random access memory, a memory structure may be formed on a substrate. The memory structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked. A protection layer including silicon nitride may be formed to cover a surface of the memory structure. The protection layer may be formed by a chemical vapor deposition process using plasma and introducing deposition gases including a silicon source gas, a nitrogen source gas containing no hydrogen and a dissociation gas. Damages of the MTJ structure may be decreased during forming the protection layer. Thus, the MRAM may have improved characteristics.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungmin Lee, Younghyun Kim, Junghwan Park, Sechung Oh, Kyungil Hong
  • Patent number: 11329053
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Patent number: 11315970
    Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: April 26, 2022
    Assignee: SONY CORPORATION
    Inventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
  • Patent number: 11315993
    Abstract: A display apparatus includes a plurality of pixels. Each pixel of the pixels includes a thin film transistor, a first insulating pattern positioned on the thin film transistor, a pixel electrode positioned on the first insulating pattern, and a second insulating pattern covering an edge of the pixel electrode and contacting an edge of the first insulating pattern.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 26, 2022
    Inventors: Yonghoon Yang, Minsuk Ko, Sikwang Kim, Taegyun Kim