Abstract: A pixel arrangement including: first groups of sub-pixels arranged in a first direction, each of the first groups including first sub-pixels and third sub-pixels arranged alternately; and second groups of sub-pixels arranged in the first direction, each of the second groups including third sub-pixels and second sub-pixels arranged alternately. The first groups and the second groups are alternately arranged in a second direction perpendicular to the first direction. The first groups and the second groups are arranged to form third groups of sub-pixels arranged in the second direction and fourth groups of sub-pixels arranged in the second direction. The third groups and the fourth groups are alternately arranged in the first direction. Each of the third groups includes first sub-pixels and third sub-pixels arranged alternately. Each of the fourth groups includes third sub-pixels and second sub-pixels arranged alternately.

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure may include: a first epitaxial layer disposed on a substrate; a bonding layer disposed on the first epitaxial layer (where the bonding layer is provided with a first through-hole to expose the first epitaxial layer); a silicon substrate disposed on a side of the bonding layer away from the first epitaxial layer (where the first epitaxial layer is bonded to the silicon substrate by the bonding layer, the silicon substrate is provided with a through-silicon-via, and the through-silicon-via communicates with the first through-hole); a silicon device disposed on the silicon substrate; and a second epitaxial layer disposed on the first epitaxial layer exposed by the first through-hole. The present disclosure can improve the quality of the second epitaxial layer, and realize the integration of a silicon device and a III-V semiconductor device.

Abstract: One or more semiconductor dice are arranged on a substrate. The semiconductor die or dice have a first surface adjacent the substrate and a second surface facing away from the substrate. Laser-induced forward transfer (LIFT) processing is applied to the semiconductor die or dice to form fiducial markers on the second surface of the semiconductor die or dice. Laser direct structuring (LDS) material is molded onto the substrate. The fiducial markers on the second surface of the semiconductor die or dice are optically detectable at the surface of the LDS material. Laser beam processing is applied to the molded LDS material at spatial positions located as a function of the optically detected fiducial markers to provide electrically conductive formations for the semiconductor die or dice.

Abstract: A device includes a substrate, at least one first dielectric layer on the substrate and including a first dielectric constant, at least one second dielectric layer on the at least one first dielectric layer and including a second dielectric constant greater than the first dielectric constant, and a dummy pattern including a first conductive pattern having a first pattern density in the at least one first dielectric layer and a second conductive pattern in the at least one second dielectric layer and comprising a second pattern density. The first pattern density is equal to or greater than the second pattern density.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

Abstract: The present disclosure relates to a display panel. More specifically, the display panel is configured to surround an opening area, includes a reflective electrode including an inclined surface, and therefore provides increased luminous efficiency.

Abstract: Provided is a display device. The display device includes: a substrate; a gate line disposed on the substrate; a transistor including a part of the gate line; and a light-emitting element connected to the transistor, in which the gate line includes a first layer including aluminum or an aluminum alloy, a second layer including titanium nitride, and a third layer including metallic titanium nitride. An N/Ti molar ratio of the metallic titanium nitride may be in a range from about 0.2 to about 0.75.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.

Abstract: A display apparatus includes: a substrate including a display area and a sensor area, wherein the display area includes a first pixel, and the sensor area includes a second pixel and a transmission portion; a sensor configured to transmit a signal through the substrate via the transmission portion, wherein the second pixel includes second thin-film transistor including a semiconductor layer, and wherein a blocking layer is disposed between the sensor and the second thin-film transistor, wherein the blocking layer covers the semiconductor layer.

Abstract: In a solid-state imaging device, a material forming an underfill part is prevented from flowing toward a side of a pixel region, shortening of a distance between an end portion of an opening of a substrate and the pixel region is enabled, and miniaturization is promoted. The device includes: an imaging element having a pixel region including a large number of pixels on one plate surface of a semiconductor substrate; a substrate provided on the surface side with respect to the imaging element and having an opening for passing light to be received by the pixel region; and an underfill part including a cured fluid and covering a connection part that electrically connects the imaging element and the substrate, in which the substrate has a groove for guiding the fluid forming the underfill part in a direction away from the surface of the imaging element.

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a memory device, and a manufacturing method and a driving method thereof. The memory device includes: a substrate; a stacked structure, where the stacked structure includes a first gate layer, a second gate layer, and interlayer isolation layers, one of the interlayer isolation layers is located between the first gate layer and the second gate layer, and another one of the interlayer isolation layers is located between the first gate layer and the substrate; and a memory structure, including a through hole penetrating the stacked structure, and a trench structure filled in the through hole. The present disclosure enables the memory device to be used as nonvolatile memory with different storage modes, thereby realizing versatility of the memory device.

Abstract: A method of manufacturing a bonded structure includes providing a first semiconductor structure including a first die, a first dielectric layer and a first conductive pad electrically connected to the first die and surrounded by the first dielectric layer; providing a second semiconductor structure including a second die, a second dielectric layer and a second conductive pad electrically connected to the second die and surrounded by the second dielectric layer; providing a carrying module including a holding unit configured to hold the second semiconductor structure and an anchoring unit movably attached to the holding unit, wherein the anchoring unit includes an end portion; disposing the carrying module and the second semiconductor structure over the first semiconductor structure; and displacing the anchoring unit towards the first semiconductor structure to make the end portion in contact with the first dielectric layer.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

Abstract: A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the display includes a plurality of pixel electrodes positioned over a substrate and separate from each other, a plurality of auxiliary wirings between the pixel electrodes, a pixel-defining layer over the pixel electrodes except for a central portion of the pixel electrodes and at least a portion of each of the auxiliary wirings, an intermediate layer over the pixel-defining layer and having a plurality of openings formed over the portion of each of the auxiliary wirings, and an opposite electrode positioned over the intermediate layer and facing the pixel electrodes, the opposite electrode electrically contacting the auxiliary wirings via the openings. The auxiliary wirings extend in a first direction and separate from each other by a first distance. The openings are aligned in a diagonal direction crossing the first direction.

Abstract: An adhesive member includes: a conductive particle layer including a plurality of conductive particles; a non-conductive layer disposed on the conductive particle layer; and a screening layer interposed between the conductive particle layer and the non-conductive layer and includes a plurality of screening members spaced apart from each other.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.