Abstract: A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.

Abstract: Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type.

Abstract: A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

Abstract: A method of manufacturing an electronic device is disclosed. An electronic unit is provided. The electronic unit has a chip and at least one bonding pin. The electronic unit is mounted on the substrate through the at least one bonding pin, and an adhesive material is applied to a space between the chip and the substrate.

Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

Abstract: A display apparatus includes: a substrate including a display area and a sensor area, wherein the display area includes a first pixel, and the sensor area includes a second pixel and a transmission portion; a sensor configured to transmit a signal through the substrate via the transmission portion, wherein the second pixel includes second thin-film transistor including a semiconductor layer, and wherein a blocking layer is disposed between the sensor and the second thin-film transistor, wherein the blocking layer covers the semiconductor layer.

Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.

Abstract: To provide a light-emitting element which uses a fluorescent material as a light-emitting substance and has higher luminous efficiency. To provide a light-emitting element which includes a mixture of a thermally activated delayed fluorescent substance and a fluorescent material. By making the emission spectrum of the thermally activated delayed fluorescent substance overlap with an absorption band on the longest wavelength side in absorption by the fluorescent material in an S1 level of the fluorescent material, energy at an S1 level of the thermally activated delayed fluorescent substance can be transferred to the S1 of the fluorescent material. Alternatively, it is also possible that the S1 of the thermally activated delayed fluorescent substance is generated from part of the energy of a T1 level of the thermally activated delayed fluorescent substance, and is transferred to the S1 of the fluorescent material.

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Abstract: A display module and a method for manufacturing thereof are provided. The display module includes a glass substrate; a thin film transistor (TFT) layer provided on a surface of the glass substrate, the TFT layer including a plurality of TFT electrode pads; a plurality of light emitting diodes (LEDs) provided on the TFT layer, each of the plurality of LEDs including LED electrode pads that are electrically connected to respective TFT electrode pads among the plurality of TFT electrode pads; and a light shielding member provided on the TFT layer and between the plurality of LEDs, wherein a height of the light shielding member with respect to the TFT layer is lower than a height of the plurality of LEDs with respect to the TFT layer.

Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: A display device includes a display panel including a display area and a non-display area defined therein and including a plurality of signal pads overlapping the non-display area, an electronic component including a base layer with an upper surface and a lower surface, a plurality of driving pads disposed on the lower surface of the base layer, and a plurality of driving bumps respectively disposed on the plurality of driving pads, the plurality of driving bumps being respectively connected to the signal pads, and a filler disposed between the display panel and the electronic component. A first hole is defined in the upper surface of the base layer, and the first hole does not overlap the plurality of driving bumps in a plan view.

Abstract: Provided is a semiconductor chip mounting tape. The semiconductor chip mounting tape comprises a tape base film including first and second surfaces opposite to each other; and an adhesive film including a third surface facing the first surface of the tape base film, and a fourth surface opposite to the third surface, wherein the adhesive film includes a plurality of voids therein, and the fourth surface of the adhesive film may be adhered to a semiconductor chip.

Abstract: A display system includes (a) a display element having an organic light emitting diode-containing display active area disposed over a silicon backplane, (b) a display driver integrated circuit (DDIC) attached to the display element and electrically connected with the display active area, and (c) a thermal barrier disposed within the silicon backplane, where the thermal barrier is configured to inhibit heat flow through the silicon backplane and into the display active area.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.

Abstract: A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.

Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

Abstract: An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.