Patents Examined by Teresa M. Arroyo
  • Patent number: 10008472
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 26, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 9890036
    Abstract: In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Charles Ehmke, Virgil Cotoco Ararao
  • Patent number: 9893237
    Abstract: A light emitting element includes a semiconductor layer; an upper electrode disposed on an upper surface of the semiconductor layer; and a lower electrode disposed on a lower surface of the semiconductor later. In a plan view, the upper electrode includes a first extending portion extending in an approximately rectangular shape along an outer periphery of the semiconductor layer, a first pad portion connected to a first side among four sides of the first extending portion, a second pad portion connected to a second side that is opposite to the first side, among the four sides of the first extending portion, and a second extending portion and a third extending portion, each disposed in a region surrounded by the first extending portion, the second extending portion and the third extending portion each connecting the first pad portion and the second pad portion.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 13, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Hidetoshi Tanaka
  • Patent number: 9870925
    Abstract: A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 16, 2018
    Inventor: Anatoly Feygenson
  • Patent number: 9871007
    Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: John G. Meyers, Bilal Khalaf, Sireesha Gogineni, Brian J. Long
  • Patent number: 9865787
    Abstract: A chip substrate includes conductive portions, insulation portions, cavities and a heat dissipating portion. The insulation portions are alternately bonded to the conductive portions to electrically isolate the conductive portions. The lens insertion portions are formed on an upper surface of the chip substrate at a predetermined depth so as to extend across each of the insulation portions. Each of the lens insertion portions includes a predetermined number of straight sides and a predetermined number of arc-shaped corners formed in regions where the straight sides meet with each other. The cavities are formed inward of the lens insertion portions at a predetermined depth so as to extend across each of the insulation portions. The heat dissipating portion is bonded to a lower surface of the chip substrate.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 9, 2018
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Seung Ho Park
  • Patent number: 9865769
    Abstract: A method of forming, and corresponding structure, of an LED device where an LED and the contacts for the device are formed on a surface of the substrate, and the substrate is spalled just below the surface of the substrate.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Stephen W. Bedell, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9859205
    Abstract: A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern. The semiconductor device further includes an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge, and an insulating layer formed on the adhesion layer, where the adhesion layer enhances adhesion of the insulating layer to the plated conductive material of the airbridge.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 2, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Timothy J. Whetten, Wayne P. Richling
  • Patent number: 9847506
    Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 19, 2017
    Assignee: LG Display Co., Ltd.
    Inventor: Jun Seok Lee
  • Patent number: 9837361
    Abstract: A semiconductor package including a semiconductor chip having an active surface and a non-active surface opposite to the active surface, a ground member disposed on the active surface of the semiconductor chip, and an electromagnetic shielding member passing through the semiconductor chip, electrically connected to the ground member, and covering at least some regions of the non-active surface of the semiconductor chip may be provided.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-rim Seo, Woon-bae Kim, Young-doo Jung
  • Patent number: 9831204
    Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 28, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Patent number: 9831396
    Abstract: A light emitting device includes a light emitting element, a molded member, and a sealing member. The light emitting element is arranged on or above the molded member. The sealing member covers the light emitting element. The sealing member contains a phosphor, and a filler material. The phosphor can be excited by light of the light emitting element, and emit luminescent radiation. The filler material contains neodymium hydroxide, neodymium aluminate or neodymium silicate. The filler material absorbs a part of the spectrum of the mixed light of the light emitting element and the phosphor so that the other parts of the spectrum of this mixed light are extracted from the light emitting device.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 28, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Shoji Hosokawa, Daiki Kuramoto, Kenji Nakata, Atsushi Bando
  • Patent number: 9825209
    Abstract: A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 21, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Mima, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Patent number: 9816682
    Abstract: A cover for a light source for use in a lamp or luminaire. An outer surface of the cover, opposite the light source, comprises a rounded shape and includes a protrusion extending from the cover. The protrusion extends substantially in a light emission direction and is shaped the protrusion to direct light emitted from the light source in a desired direction.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 14, 2017
    Assignee: BRIDGELUX INC.
    Inventor: Xiaolu Chen
  • Patent number: 9786583
    Abstract: A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 10, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, De Mei Gong
  • Patent number: 9786601
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: October 10, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Patent number: 9786815
    Abstract: A light-emitting device is disclosed. The light-emitting device comprises a substrate; an inorganic semiconductor formed on the substrate, comprising a top surface, wherein the top surface comprises a first region and a second region which are coplanar; a current barrier layer formed on the first region, wherein the current barrier layer comprises an insulating material; and a transparent conductive layer formed on the current barrier layer and contacting the second region; wherein the current barrier layer has a sidewall and a bottom surface facing the first region; wherein an angle between the sidewall and the bottom surface is between 10°-70°.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 10, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Jar-Yu Wu, Ching-Jang Su, Chun-Lung Tseng, Ching-Hsing Shen
  • Patent number: 9780054
    Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Javier Soto Gonzalez, Nicholas R. Watts, Ravi K Nalla
  • Patent number: 9768269
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 9761567
    Abstract: A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an insulating substrate in a housing. A resin provided in the housing covers the wiring member, and has a height in the vicinity of the wiring member. A cover covering the periphery of external terminals is provided between the resin and a first lid in the housing. A second lid is provided further outside the first lid in an aperture portion of the housing, and the space between the second lid and the first lid is filled with another resin.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda