Patents Examined by Teresa Maria Arroyo
-
Patent number: 5854508Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: March 19, 1996Date of Patent: December 29, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
-
Patent number: 5847451Abstract: In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.Type: GrantFiled: September 25, 1996Date of Patent: December 8, 1998Inventors: Toru Ohtaki, Yasuteru Ichida, Yasushi Takeuchi
-
Patent number: 5838062Abstract: A lead frame for a semiconductor chip package, including a die pad onto which a semiconductor chip will be attached; leads which will be electrically connected to the chip; and side rails supporting the leads and the die pad; a second metal being contact with the rails, this second metal having a higher standard electrode potential than that of the copper metal or alloy of which the remainder of the lead frame is made.Type: GrantFiled: March 26, 1996Date of Patent: November 17, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Youn Hwang, Hee Suck Kim, Jae Won Lee
-
Patent number: 5828129Abstract: A semiconductor memory device suitable for forming a capacitor using a high dielectric film for a highly integrated semiconductor device includes a semiconductor substrate, an insulating film having a contact hole, the insulating film being over the semiconductor substrate, a conductive film on the semiconductor substrate through the contact hole, the conductive film having a top portion acting as a diffusion barrier, a first electrode over the conductive films, a dielectric film over the first electrode, and a second electrode over the dielectric film.Type: GrantFiled: January 23, 1997Date of Patent: October 27, 1998Assignee: LG Semicon Co., Ltd.Inventor: Jae Sung Roh
-
Patent number: 5814535Abstract: An electronic package according to the present invention comprises a supporting member, an electronic device, a carrier, a substrate and cooling means. The supporting member includes a plate and a bottom leg for supporting the plate. A first end of the bottom leg is joined to the lower surface of the plate. The carrier has a hole for receiving the bottom leg. The electronic device is connected to the carrier and is attached to the lower surface of the plate. A second end of the bottom leg is inserted into the hole of the carrier. The second end of the bottom leg is joined to the upper surface of the substrate. The electronic device is positioned between the plate of the supporting member and the substrate. The cooling means is attached onto and supported by the upper surface of the plate.Type: GrantFiled: December 15, 1995Date of Patent: September 29, 1998Assignee: NEC CorporationInventors: Yuzo Shimada, Takayuki Suyama, Yoshimasa Tanaka
-
Patent number: 5801451Abstract: A control signal applied to a lead terminal is transmitted to metal wires and bonding pads. The control signal arriving at the bonding pads are provided at high speed from the lead terminal to the input nodes of input buffer circuits via interconnection layers with almost no difference in the signal transmission time delay. The input buffer circuits can be disposed in close proximity to a desired circuit controlled by the same control signal and also in close proximity to any of the bonding pads. The length of the interconnection layers for connecting an input node of an input buffer circuit with a corresponding bonding pad can be reduced, so that the difference in the signal transmission time delay can be neglected. Thus, a high speed semiconductor device is provided that can have the signal delay difference of a control signal applied to the input buffers reduced.Type: GrantFiled: November 26, 1997Date of Patent: September 1, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tadaaki Yamauchi
-
Patent number: 5798569Abstract: In a semiconductor device having a metal wiring conductor connected to a contact hole formed through an interlayer insulator layer formed on a lower level circuit, a lower level tungsten film is deposited under a condition giving an excellent step coverage so as to fill the contact hole, and an upper level tungsten film is further deposited under a condition of forming a film having a stress smaller than that of the lower level tungsten film. The metal wiring conductor is formed of a double layer which is composed of the lower level tungsten film and the upper level tungsten film, and therefore, has a reduced stress in the whole of the film. Thus, there is obtained the tungsten film wiring conductor which fills the inside of the contact hole with no void and therefore has a high reliability, and which has a low film stress. In addition, the number of steps in the manufacturing process can be reduced.Type: GrantFiled: July 17, 1997Date of Patent: August 25, 1998Assignee: NEC CorporationInventors: Kazuki Miyazaki, Kazunobu Shigehara, Masanobu Zenke
-
Patent number: 5793101Abstract: A package housing multiple semiconductor die includes a leadframe having a paddle and a number of lead fingers. A flexible circuit is adhesively laminated to both sides of the paddle. A first semiconductor die is back-mounted to the bottom surface of the paddle and wire-bonded to the flexible circuit and the lead fingers. A second semiconductor die is back-mounted to the top surface of the paddle and to the flexible circuit. The dies are encapsulated in a security coating and encased in plastic.Type: GrantFiled: January 21, 1997Date of Patent: August 11, 1998Assignee: Intel CorporationInventor: Harry A. Kuhn
-
Patent number: 5773884Abstract: An electronic package which includes a rigid support member, e.g., copper sheet, to which is bonded both the package's semiconductor chip and circuitized substrate members. The chip is bonded using a thermally conductive adhesive while the circuitized substrate, preferably a flexible circuit, is bonded using an electrically insulative adhesive. The chip is electrically coupled to designated parts of the circuitry of the substrate, preferably by wire, thermocompression or thermosonic bonding. An encapsulant may be used to cover and protect the connections between the chip and substrate. This package may in turn be electrically coupled to a separate, second substrate such as a PCB.Type: GrantFiled: March 3, 1997Date of Patent: June 30, 1998Assignee: International Business Machines CorporationInventors: Frank Edward Andros, James Russell Bupp, Michael DiPietro, Richard Benjamin Hammer
-
Patent number: 5528081Abstract: A contact and interconnect structure for a semiconductor integrated circuit includes a thin layer of refractory metal on a contact surface of the substrate through an opening in an overlying insulation layer with boron ions implanted into the substrate through the layer of refractory metal and the contact surface to ensure a uniform ohmic contact. An interconnect structure is then formed on the insulation layer and on the thin layer of refractory metal including a first layer of a refractory metal nitride on the insulation layer, a second layer of refractory metal on the first layer of refractory metal nitride, and a second layer of refractory metal nitride on the second layer of refractory metal.Type: GrantFiled: January 18, 1995Date of Patent: June 18, 1996Inventor: John H. Hall
-
Patent number: 5408120Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density i.sub.H -layer. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.Type: GrantFiled: January 22, 1993Date of Patent: April 18, 1995Assignees: Toyoda Gosei Co., Ltd., Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Katsuhide Manabe, Masahiro Kotaki, Makoto Tamaki, Masafumi Hashimoto