Multi-layered printed circuit board, and grid array package adopting the same
In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.
Claims
1. A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, sa d LSI having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said circuit board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said LSI; and
- a power supply pattern formed on said circuit board, said power supply pattern being connected to the other end of said inductance pattern.
2. A circuit board according to claim 1, wherein said inductance pattern is formed on an inner layer of said circuit board.
3. A circuit board according to claim 1, wherein through hole lands connected to the plurality of power supply pins are formed on said power supply pattern, a notch is formed to surround a predetermined range including some or all of said through hole lands, and a portion surrounded by the notch is connected at least at one position to said power supply pattern via said inductance pattern.
4. A circuit board according to claim 3, wherein said inductance pattern is disposed at a position in the vicinity of a signal line connected to a signal pin, which receives a clock signal having a periodicity, of the plurality of signal pins.
5. A circuit board according to claim 1, wherein said inductance pattern has a parallel shape.
6. A circuit board according to claim 1, wherein said inductance pattern has a spiral shape.
7. A circuit board according to claim 1, wherein said inductance pattern constitutes a low-pass filter together with a capacitor element arranged in the vicinity thereof.
8. A circuit board according to claim 1, wherein said capacitor element is formed by a circuit pattern.
9. A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, said LSI having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed on a signal layer of said circuit board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said LSI;
- a power supply pattern formed on a power supply layer of said circuit board; and
- a through hole for connecting said power supply pattern and the other end of said inductance pattern.
10. A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, said LSI having a plurality of power supply pins and a plurality of ground pins;
- an inductance pattern formed on a first layer of said circuit board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said LSI;
- a power supply pattern formed on a second supply layer of said circuit board;
- a first through hole for connecting said inductance pattern and the other end of said power supply pattern;
- a ground pattern formed on a third layer of said circuit board; and
- a second through hole for connecting said ground pattern and the ground pins.
11. A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, said LSI having a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said circuit board, one end of said inductance pattern being connected to a predetermined pin of the plurality of signal pins of said LSI; and
- a signal line pattern formed on said circuit board, said signal line pattern being connected to the other end of said inductance pattern.
12. A circuit board according to claim 11, wherein said inductance pattern has a parallel shape.
13. A circuit board according to claim 11, wherein said inductance pattern has a spiral shape.
14. A circuit board according to claim 11, wherein said inductance pattern constitutes a low-pass filter together with a capacitor element arranged in the vicinity thereof.
15. A circuit board according to claim 11, wherein said capacitor element is formed by a circuit pattern.
16. A grid array package which adopts a multi-layered printed circuit board, comprising:
- a semiconductor chip mounted on said package, said semiconductor chip having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said package, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said semiconductor chip; and
- a power supply pattern formed on said package, said power supply pattern being connected to the other end of said inductance pattern.
17. A package according to claim 16, wherein said inductance pattern has a parallel shape.
18. A package according to claim 16, wherein said inductance pattern has a spiral shape.
19. A package according to claim 16, wherein said inductance pattern constitutes a low-pass filter together with a capacitor element arranged in the vicinity thereof.
20. A package according to claim 19, wherein said capacitor element is formed by a circuit pattern.
21. A grid array package comprising:
- a semiconductor chip mounted on a package board, said semiconductor chip having a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said package board, one end of said inductance pattern being connected to a predetermined pin of the plurality of signal pins of said semiconductor chip; and
- a signal line pattern formed on said package board, said signal line pattern being connected to the other end of said inductance pattern.
22. A package according to claim 21, wherein said inductance pattern has a parallel shape.
23. A package according to claim 21, wherein said inductance pattern has a spiral shape.
24. A package according to claim 21, wherein said inductance pattern constitutes a low-pass filter together with a capacitor element arranged in the vicinity thereof.
25. A package according to claim 24, wherein said capacitor element is formed by a circuit pattern.
26. A grid array package comprising:
- a semiconductor chip mounted on a first layer of a package board, said semiconductor chip having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed on a second layer of said package board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said semiconductor chip;
- a power supply pattern formed on the second layer of said package board, said power supply pattern being connected to one end of said inductance pattern; and
- a through hole for connecting the other end of said power supply pattern and at least one of the plurality of power supply pins.
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Type: Grant
Filed: Sep 25, 1996
Date of Patent: Dec 8, 1998
Inventors: Toru Ohtaki (Ohta-ku, Tokyo), Yasuteru Ichida (Ohta-ku, Tokyo), Yasushi Takeuchi (Ohta-ku, Tokyo)
Primary Examiner: Teresa Maria Arroyo
Application Number: 8/721,793
International Classification: H01L 2348; H01L 2900; H01L 29053; H01L 2334;
