Abstract: Selected domains, normally 2×103×2×103 such domains arrayed in a plane, within a three-dimensional (3-D) volume of radiation-sensitive medium, typically 1 cm3 of spirobenzopyran containing 2×103 such planes, are temporally and spatially simultaneously illuminated by two radiation pulses, normally laser light pulses in various combinations of wavelengths 532 nm and 1024 nm, in order, dependent upon the particular combination of illuminating light, to either write binary data to, or read binary data from, the selected domains by process of two-photon (2-P) interaction/absorption. One laser light pulse is preferably directed to illuminate all domains during its propagation along one directional axis of the volume. The other laser light pulse is first spatially encoded with binary information by 2-D spatial light modulator, and is then (i) directed and (ii) time sequenced to intersection with the other light pulse in a locus of intersection domains.
May 30, 1995
Date of Patent:
August 19, 2003
The Regents of the University of California
Abstract: A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.
Abstract: Three-, and four-dimensional (“3-D” and “4-D”) volume radiation memories store multiple binary bits of information—typically about five to ten and more typically eight such bits—in the same physical volumes on several different photochromic chemicals co-located in the volume. Each of the multiple photochromic chemicals is individually selectively written with an individually associated pair of radiation beams of an appropriate combined frequency—i.e., a “color”—and energy by a process of two-photon (“2-P”) absorption. All the multiple information bits that are stored within all the photochromic chemicals in each addressable domain are read in common, and induced to simultaneously fluoresce, again by process of 2-P absorption.
June 7, 1995
Date of Patent:
November 19, 2002
The Regents of the University of California
Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
Abstract: Programmable devices and methods of programming programmable devices are described. In one embodiment, a complex programmable logic device (CPLD) is programmed by a remote host programming unit that provides the configuration data over a data communications link into a first data-holding location on the device all at one time. The device is then locally programmed under the influence of a controller that causes the configuration data in the first data-holding location to be written or copied to a second data-holding location on the device. In one embodiment, the first data-holding location is a rapidly programmed temporary memory (e.g., RAM), while the second data-holding location is a non-volatile memory that takes much longer to program (e.g., EEPROM or flash memory) and actually controls the device functionality. This technique frees up the host programming unit and the data communications link to attend to other matters, such as providing configuration data to other programmable devices.
Abstract: A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column.
Abstract: An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.
March 16, 2001
Date of Patent:
May 28, 2002
Virage Logic Corporation
Niranjan Behera, Shreekanth K. Sampigethaya
Abstract: To efficiently access pixel data stored in memory in the X direction and Y direction when carrying out error correction processing. In a data output section 10, a pixel block consisting the desired 2×2 pixel data W1-W4 is selected by inputting a address, and pixel data continuously aligned in an arbitrary direction, that is, in the X direction or Y direction, are output inputting output pixel selection signals V1 and V2. Specifically, two pixels W1, W2, or W3, W4, which are continuously aligned in the X direction, are selected when signals V1 and V2=0 and V1=0 and V2=1, and two arbitrary pixels W1, W3 or W2, W4, which are continuously aligned in the Y direction, are selected when signal V1=1 and V2=0 and V1 and V2=1.
Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.
Abstract: The present invention provides novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. The novel EPROM device can be manufactured by applying the manufacturing processes used for making dynamic random access memory (DRAM), standard logic technologies or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. The EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for the programmable firmware for logic products, and the security identification circuits for IC products.
Abstract: A method and apparatus for dynamically determining when a bias circuit has reached a steady-state operation so that the memory elements (e.g., EPROMs) may be read. The bias circuit includes a read enable circuit, a bias circuit, and an output circuit. The bias circuit is configured to dynamically detect a memory element bias voltage in response to a read enable signal, which is provided by the read enable circuit. The memory element bias voltage varies from an initial voltage to a final voltage based on the amount of loading due to the memory elements (e.g., EPROMs). The bias circuit outputs a read signal when the memory element bias voltage reaches the final voltage. The memory elements initiate reading data that is stored in the memory elements in response to the read signal. The bias circuit may include a bias generator, a memory element driver and a detector. The bias generator is configured to generate an internal bias voltage.
Abstract: Logical block addresses are allocated to the blocks provided on a flash memory, respectively. Address translation tables (LTPb's) are provided on the flash memory, each for a group of blocks. Groups of logical block addresses are provided, each group for one group of blocks provided on the flash memory. The logical block addresses of each group have a specific field each. The same data item is contained in the specific fields of the logical block addresses of any group. The data item designates all blocks of the group corresponding to the group of the logical block addresses. Each table has a group of entries storing physical address information indicating the locations that the blocks take in the flash memory. At least one of the tables is stored on a RAM. When a logical address is given from a host system, a microprocessor determines whether a table corresponding to the logical address exists on the RAM. If such table does not exist, the table is copied from the flash memory to the RAM.
Abstract: A semiconductor memory of the dynamic random access type (DRAM) includes memory cells combined in addressable units of bit lines and word lines. Each memory cell array is allocated a row decoder for selection of one of the word lines and a column decoder for selection of one of the bit lines, in the memory cell array. The row decoder is connected to a row selection signal line for transmission of a selection signal. The row decoder is disposed at an edge of the memory cell array allocated thereto, and between the memory cell arrays. The column decoder is connected to the row selection signal line. The column decoder is disposed on the outer edge area both of the memory cell array allocated thereto and of the memory field. A method for actuating a memory cell in such a semiconductor memory is also provided.
Abstract: An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock pulses, outputs carry signal when the row counter count to B−1, outputs the 0 value when the first row address is outputting, outputs the added value of offset value F and previous output value of the row counter, and generates a counter reset signal when output the carry signal. The B is the number of rows. A column counter increases a count value in increments of one in response to the carry signal. A mapper permutates the output of the counter according to a predetermined permutation rule. An adder generates a read address by using the output of the row counter as the most significant bits(MSB) of the read address and by using the output of the mapper as the least significant bits(LSB) of the read address.
Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.
Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.
January 10, 2000
Date of Patent:
March 12, 2002
Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.
Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.
Abstract: A method of reading data from a ferroelectric memory has a memory cell which uses a ferroelectric capacitor as a storage medium. The method includes the steps of (a) applying first and second electric fields having opposite directions to the ferroelectric capacitor, wherein polarization of the ferroelectric capacitor is changed according to a variation of the first and second electric fields; and (b) reading out the data stored in the memory cell by detecting a variation of the polarization of the ferroelectric capacitor.
Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signals which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.
Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.