Patents Examined by Than Nguyen
  • Patent number: 10379765
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Patent number: 10379740
    Abstract: Provided are a computer program product, system, and method for using mirror indicators to indicate whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume. A table includes a mirror indicator for each of a plurality of tracks in at least one data set in the primary volume indicating whether a track is to be mirrored to the secondary volume. In response to a write command of write data for one of the tracks in the primary volume, creating a record set in a cache for the primary volume including write data for the track to transfer to the secondary volume in response to the mirror indicator for the track indicating that the track is to be mirrored. The write data in the record set is transferred from the cache to the secondary volume.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory E. McBride, Dash D. Miller, Miguel A. Perez, David C. Reed
  • Patent number: 10379738
    Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
  • Patent number: 10365854
    Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Ashutosh Malshe, Sampath Ratnam, Harish Singidi, Vamsi Pavan Rayaprolu
  • Patent number: 10365828
    Abstract: A technique for efficiently storing compressed data of a storage object in a data storage includes (a) receiving, in a cache buffer, a number, U, of uncompressed blocks of a uniform size, the uncompressed data blocks received in write requests directed to the storage object; (b) compressing the uncompressed blocks of the cache buffer into respective compressed extents; (c) performing an optimization operation including generating a set of distributions of compressed extents among a plurality of containers and searching the set for a distribution having a minimal total amount of storage taken up by its respective plurality of containers, each container having a respective size equal to a respective integer multiple of the uniform size of the uncompressed data blocks; and (d) storing the compressed extents within a plurality of containers in persistent storage in accordance with the distribution having the minimal total amount of storage taken up by its respective plurality of containers.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 30, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Ivan Bassov
  • Patent number: 10365997
    Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a memory access latency value including a time to perform an operation with respect to the memory bank of the plurality of memory banks, receiving a set of operation percentages including an operation percentage for each of a plurality of operations performed on the memory bank, determining a probability associated with the memory access latency value using a mixture of Weibull distributions, described herein, comparing the probability to a threshold probability to provide a comparison, and selectively executing at least one action with respect to the memory bank based on the comparison.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: July 30, 2019
    Assignee: Hybris AG
    Inventor: Ahmad Hassan
  • Patent number: 10360054
    Abstract: File mapping and converting for dynamic disk personalization for multiple platforms are provided. A volatile file operation is detected in a first platform. The file supported by the first platform. A determination is made that the file is sharable with a second platform. The volatile operation is performed on the file in the first platform and the modified file is converted to a second file supported by the second platform. The modified file and second file are stored in a personalized disk for a user. The personalized disk is used to modify base images for VMs of the user when the user accesses the first platform or second platform. The modified file is available within the first platform and the second file is available within the second platform.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: July 23, 2019
    Assignee: Micro Focus Software Inc.
    Inventors: Nathaniel Brent Kranendonk, Jason Allen Sabin, Lloyd Leon Burch, Jeremy Ray Brown, Kal A. Larsen, Michael John Jorgensen
  • Patent number: 10353817
    Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory W. Alexander, Brian D. Barrick, Thomas W. Fox, Christian Jacobi, Anthony Saporito, Somin Song, Aaron Tsai
  • Patent number: 10353605
    Abstract: Whether a replication relationship is established between a first and a second storage device is determined. If it is determined that the replication relationship is established between the first and second storage device, then whether data in the first region of the first storage device has changed since a previously completed asynchronous data replication process is determined. If the data in the first region of the first storage device has changed since the previously completed asynchronous data replication process, then whether the changed data in the first storage device is data copied from the second region of the first storage device is determined. If the changed data in the first region of the first storage device is data copied from the second region of the first storage device, then data from the second region of the second storage device is replicated to the first region of the second storage device.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manish Bansode, Shrirang S. Bhagwat, Pankaj Deshpande, Subhojit Roy
  • Patent number: 10353641
    Abstract: A storage system includes a plurality of storage media and a method of managing volumes of the storage system is applied thereto. The method includes receiving a volume management request and correlation information between the volumes, and allocating storage spaces of the storage media to the volumes based on the correlation information between the volumes. The correlation information indicates information of the volumes in which the allocated storage media are physically isolated from each other.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Min Seo
  • Patent number: 10353597
    Abstract: A method for transferring memory pages to a first and a second page repository identifies pages in a memory sharing operation for transfer to a first page repository and pages in a memory migration operation for transfer to a second page repository. Pages in the memory migration operation may be prepared for transfer prior to transfer of the pages in the memory sharing operation. Transferring pages in the migration operation may remove the need to transfer pages in the memory sharing operation.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Swetha N. Rao
  • Patent number: 10353454
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, a second memory, and a controller. The processing device is configured to process first data. The first memory is configured to store at least part of the first data and has an active region supplied with power necessary for holding data. The second memory is configured to store part of the first data. The controller is configured to change number of active regions such that processing information is not more than a threshold. The processing information indicates an amount of processing for moving at least part of second data stored in the first memory to the second memory and for moving at least part of third data stored in the second memory to the first memory, in a certain period for processing the first data having a size larger than active regions.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura, Satoshi Shirai
  • Patent number: 10339043
    Abstract: An apparatus, system, and method is described for calculating a composite index into a customizable hybrid address space that is at least partially compressed to locate a longest prefix match (“LPM”) of a prefix string comprised of a plurality of multi-bit strides (“MBSs”). The device comprises: a mask-and-count logic for generating a base index into memory for a first MBS whose addresses are not compressed; a logical-shift apparatus that selectively uses a variable portion of the second MBS to generate an offset index from the given base index per an amount the second MBS addresses were actually compressed; and an add logic that adds the base index to the offset index to form the composite index that locates the LPM using a single access into memory. A compressed vector contains compression information of the second MBS in an information density format greater than a single bit to a single address.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 2, 2019
    Assignee: MoSys, Inc.
    Inventor: Michael J Miller
  • Patent number: 10331385
    Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Andrzej Jakowski, Maciej Kaminski
  • Patent number: 10324655
    Abstract: A method to more efficiently utilize data structures in an asynchronous data replication system is disclosed. In one embodiment, such a method includes maintaining, in memory of a primary storage system, a set of data structures for mirroring updates from the primary storage system to a secondary storage system. Each data structure has a status of either active or inactive. The method further establishes an upper threshold and lower threshold for each data structure. The method receives, into active data structures, updates that need to be mirrored to the secondary storage system. When updates in each of the active data structures reaches the upper threshold, the method activates a deactivated data structure. When updates in an active data structure fall below the lower threshold, the method deactivates and drains the data structure. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gregory E. McBride, David C. Reed, Warren K. Stanley
  • Patent number: 10318190
    Abstract: Provided are a computer program product, system, and method for using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume. A table is read. The table is maintained by a primary controller managing the primary volume that includes a mirror indicator for each of a plurality of tracks in at least one data set configured in the primary volume indicating whether a track is to be mirrored to the secondary volume. Record sets are read from a cache of the primary controller for the tracks in primary volume having the mirror indicators in the table indicating that the track is to be mirrored. The write data in the read record sets is applied to tracks in the secondary volume mirroring the tracks in the primary volume.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory E. McBride, Dash D. Miller, Miguel A. Perez, David C. Reed
  • Patent number: 10318417
    Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Lu, Karthik Kumar, Francesc Guim Bernat, Thomas Willhalm
  • Patent number: 10303361
    Abstract: A memory system may include: a memory system may include: a memory device suitable for storing user data and corresponding metadata; and a controller including a memory, the controller being suitable for storing user data and corresponding metadata in the memory and for controlling the memory device for storing therein the user data and the metadata of the memory when sizes of the user data and metadata of the memory reach first and second thresholds, respectively.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventor: Gi-Pyo Um
  • Patent number: 10303555
    Abstract: In one approach, data blocks or files that have a history of change are tagged for automatic transfer to backup on the assumption that they have changed since the last backup. Other data blocks and files are first tested for change, for example by comparing digital fingerprints of the current data versus the previously backed up data, before transferring to backup.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: May 28, 2019
    Assignee: RUBRIK, INC.
    Inventor: Looi Chow Lee
  • Patent number: 10298684
    Abstract: Adaptive replication of data in a dispersed storage network (DSN) to improve data access performance. In various examples, a DSN storage unit determines that a frequency of slice access of an encoded data slice stored by the storage unit compares unfavorably to a first slice access threshold (e.g., a greater number of accesses than a threshold number of accesses over a given period of time). The storage unit then identifies at least one secondary storage unit and replicates the encoded data slice to generate a replicated encoded data slice. The replicated encoded data slice is then sent to the at least one secondary storage unit for storage therein. In addition, a slice storage location table is updated to associate the at least one secondary storage unit and the replicated encoded data slice such that future access requests for the encoded data slice may be re-directed to a secondary storage unit.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Baptist, S. Christopher Gladwin, Jason K. Resch