Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

Abstract: A method, computer program product, and computing system for processing a first data access request from a first computing device for accessing a cloud storage portion of a plurality of cloud storage portions associated with a cloud-based storage resource. A current ownership sequence identifier associated with the cloud storage portion is obtained. The current ownership sequence identifier from the cloud storage portion is compared to a previously obtained ownership sequence identifier for the cloud storage portion on the first computing device. The first data access request is effectuated on the cloud storage portion when the current ownership sequence identifier is identical to the previously obtained ownership sequence identifier.

Abstract: The disclosed technology provides instructions to manipulate the state of a processor's cache. An application may send an instruction directly to the processor, providing it with information about memory allocation or deallocation events occurring within the application. This direct communication facilitates immediate synchronization between the application and the processor, ensuring accurate memory management.

Abstract: A storage operation support apparatus includes a storage unit that stores storage device information that stores information on a state of a storage device and an evaluation unit that evaluates an evaluation target storage device to be evaluated. With reference to the storage device information, the evaluation unit calculates an environment score indicating a magnitude of a load on an environment of the evaluation target storage device, calculates a cost score indicating a magnitude of a cost of the evaluation target storage device, calculates a performance score indicating a slow speed of reading and writing data of the evaluation target storage device, and calculates a total score using the environment score, the cost score, and the performance score.

Abstract: A multilevel-cache-based data processing method is provided, which is applied to a server computing device. The server computing device includes a first-level cache and a second-level cache. The first-level cache includes a plurality of first-type storage nodes. The second-level cache includes a plurality of second-type storage nodes. The data processing method includes identifying a target node based on a current hash ring in response to receiving a read request; determining whether the target node is any one of the plurality of first-type storage nodes; and in response to determining that the target node is not any one of the plurality of first-type storage nodes, reading response data from the plurality of second-type storage nodes for responding to the read request, and returning the response data. According to the method, a speed of responding to the read request can be increased, and pressure of the first-level cache can be reduced.

Abstract: Computer-implemented methods for storing data with replicated metadata in a scale-out data storage system are provided. Aspects include receiving, by a first data storage node of the scale-out data storage system, a data item to be stored and storing, by the first data storage node, the data item on a storage area network in communication with the scale-out data storage system. Aspects also include generating, by the first data storage node, a metadata item corresponding to the data item and replicating the metadata item on a second data storage node of the scale-out data storage system.

Abstract: One embodiment provides for a non-transitory machine-readable medium storing instructions to cause one or more processors to perform operations comprising receiving an instruction to dynamically allocate memory for an object of a data type and dynamically allocating memory for the object from a heap instance that is specific to the data type for the object, the heap instance including a memory allocator for the data type, the memory allocator generated at compile time for the instruction based on a specification of the data type for the heap instance.

Abstract: A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.

Abstract: An electronic system includes a plurality of master devices, a memory controller and a memory device. The master devices generate requests for memory access operations, where each request includes locality information indicating whether requests are to be executed continuously. The memory controller receives the requests from the plurality of master devices, determines an execution order of the requests based on the locality information, and sequentially generates commands to perform the memory access operations according to the execution order. The memory device receives the commands from the memory controller and performs the memory access operations based on the commands.

Abstract: A prefetch unit includes multiple memories; and a memory controller coupled to the multiple memories. The memory controller includes a prefetch stream filter and a prefetch buffer. The prefetch stream filter includes a first set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots of the first set of address slots. The prefetch buffer includes a set of buffer slots, each slot of the set of buffer slots including an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots configured to store data, wherein each address field of each slot of the set of buffer slots is configured to store at least a portion of an address associated with the corresponding slot.

Abstract: A method, comprising: generating a plurality of combined utilization vectors, each of the plurality of combined utilization vectors corresponding to a different one of a plurality of port pairs; updating the plurality of combined utilization vectors based on an expected usage of the storage entity to produce a plurality of updated utilization vectors; selecting one of the plurality of port pairs based on the plurality of updated utilization vectors; and assigning the selected port pair to the replication of data that is stored in the storage entity.

Abstract: A controller of a storage device receives a stream of data from a host system. The stream of data corresponds to logical block addresses. The controller writes the stream of data to data block(s) in a device memory, each data block including respective super word line(s), each super word line including respective word line(s), and each word line corresponding to at least one logical block address. The controller generates a table for storing the logical block addresses in the order of data arrival. In response to receiving an update to one or more logical block addresses of the data block(s), the controller defragments at least one data block, based on the one or more logical block addresses, and writes data for one or more super word lines of the at least one data block to a new data block, based on the table, to retain the order.

Abstract: An electronic device includes an input handling circuit, a control circuit, and a data transfer circuit. The input handling circuits receives a first request including an address from a first memory device, aligns the address with an access unit of a second memory device, requests a determination for the aligned address, and transmits a second request to the second memory device based on a determination result. The control circuit determines, based on the request, whether a duplicate address with the aligned address is present to generate the determination result and updates a bitmask based on the determination result. The data transfer circuit receives the second request from the second memory device and transfers data based on the bitmask. The bitmask includes one or more bits, each corresponding to the first request and indicating a location corresponding to the first request within an access unit of the second memory device.

Abstract: A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.

Abstract: The present disclosure discloses a data processing apparatus, a data processing method, and related products. The data processing apparatus is used as a computing apparatus and is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is respectively connected to the computing apparatus and other processing apparatus and is used to store data of the computing apparatus and other processing apparatus. The solution of the present disclosure takes full advantage of parallelism among different storage units to improve utilization of each functional component.

Abstract: According to an embodiment of the present technology, an electronic device may include a host device including: an application requesting to write data; and a file system configured to generate, in response to the request of the application, a log regarding a property of data, and allocate a section corresponding to the data based on the log; and a storage device comprising: a memory device including a plurality of memory dies; and a memory controller configured to control the memory device to receive the data and the log of the data from the host device, and sequentially store the data in a physical zone corresponding to the section.

Abstract: Systems and methods described herein can involve for receipt of an addition or modification of a storage device, executing a validation process from one or more managed validation kits according to a remote copy function associated with the storage device, the one or more managed validation kits selected according to one or more feature types associated with the remote copy function; associating the storage device with a corresponding group of storage devices associated with the remote copy function based on information provided by the one or more managed validation kits; and for the association of the storage device with the corresponding group of storage devices and the execution of the validation process being successful, registering the storage device to a storage class associated with the remote copy function.

Abstract: A policy level controller coordinates a scheduling and policy engine using a data change metric to dynamically schedule or re-define policies in response to data change rates in data assets in a current backup session. A supervised learning process trains a model using historical data of backup operations of the system to establish past data change metrics for corresponding backups processing the saveset, and modifies policies dictating the backup schedule by determining a data change rate of received data, as expressed as a number of bytes changed per unit of time. In response to input from backup targets regarding present usage, it then modifies the backup schedule to minimize the impact on backup targets that may be at or close to overload conditions.

Abstract: Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.

Abstract: The present disclosure is directed toward systems, methods, and non-transitory computer readable media for generating and maintaining an intelligent, web-based digital content clipboard for viewing and performing batch actions on copied content items. In particular, based on a client device request to copy a content item from a web-based folder, the disclosed systems can generate and add an item reference for the copied content item to a batch action clipboard. The disclosed systems can perform batch actions on multiple digital content items together with a single web-based batch action. The disclosed systems can also intelligently provide a clipboard element for display that is selectable to view item references representing content items copied to the batch action clipboard, along with a set of available batch actions for performing on one or more of the copied content items.