Patents Examined by Than Nguyen
  • Patent number: 10324655
    Abstract: A method to more efficiently utilize data structures in an asynchronous data replication system is disclosed. In one embodiment, such a method includes maintaining, in memory of a primary storage system, a set of data structures for mirroring updates from the primary storage system to a secondary storage system. Each data structure has a status of either active or inactive. The method further establishes an upper threshold and lower threshold for each data structure. The method receives, into active data structures, updates that need to be mirrored to the secondary storage system. When updates in each of the active data structures reaches the upper threshold, the method activates a deactivated data structure. When updates in an active data structure fall below the lower threshold, the method deactivates and drains the data structure. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gregory E. McBride, David C. Reed, Warren K. Stanley
  • Patent number: 10318190
    Abstract: Provided are a computer program product, system, and method for using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume. A table is read. The table is maintained by a primary controller managing the primary volume that includes a mirror indicator for each of a plurality of tracks in at least one data set configured in the primary volume indicating whether a track is to be mirrored to the secondary volume. Record sets are read from a cache of the primary controller for the tracks in primary volume having the mirror indicators in the table indicating that the track is to be mirrored. The write data in the read record sets is applied to tracks in the secondary volume mirroring the tracks in the primary volume.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory E. McBride, Dash D. Miller, Miguel A. Perez, David C. Reed
  • Patent number: 10318417
    Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Lu, Karthik Kumar, Francesc Guim Bernat, Thomas Willhalm
  • Patent number: 10303361
    Abstract: A memory system may include: a memory system may include: a memory device suitable for storing user data and corresponding metadata; and a controller including a memory, the controller being suitable for storing user data and corresponding metadata in the memory and for controlling the memory device for storing therein the user data and the metadata of the memory when sizes of the user data and metadata of the memory reach first and second thresholds, respectively.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventor: Gi-Pyo Um
  • Patent number: 10303555
    Abstract: In one approach, data blocks or files that have a history of change are tagged for automatic transfer to backup on the assumption that they have changed since the last backup. Other data blocks and files are first tested for change, for example by comparing digital fingerprints of the current data versus the previously backed up data, before transferring to backup.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: May 28, 2019
    Assignee: RUBRIK, INC.
    Inventor: Looi Chow Lee
  • Patent number: 10298684
    Abstract: Adaptive replication of data in a dispersed storage network (DSN) to improve data access performance. In various examples, a DSN storage unit determines that a frequency of slice access of an encoded data slice stored by the storage unit compares unfavorably to a first slice access threshold (e.g., a greater number of accesses than a threshold number of accesses over a given period of time). The storage unit then identifies at least one secondary storage unit and replicates the encoded data slice to generate a replicated encoded data slice. The replicated encoded data slice is then sent to the at least one secondary storage unit for storage therein. In addition, a slice storage location table is updated to associate the at least one secondary storage unit and the replicated encoded data slice such that future access requests for the encoded data slice may be re-directed to a secondary storage unit.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Baptist, S. Christopher Gladwin, Jason K. Resch
  • Patent number: 10289317
    Abstract: A method of wear leveling receives a write request. The write request indicates received data to be written to memory blocks. The method detects a system condition. Example system conditions include a random write condition, a garbage collection start condition, and/or a sequential write condition. Based on the system condition, the method determines whether the received data comprises hot data or cold data. Some embodiments use a write amplification value to determine the system condition. If the received data comprises hot data, the method writes the received data to a cold block. If the received data comprises cold data, the method writes the received data to a hot block.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: May 14, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ming-Yu Tai, Subhash Balakrishna Pillai, Yung-Li Ji, Haining Liu
  • Patent number: 10261712
    Abstract: Method and system are provided for storage capacity allocation. The method includes: providing a storage pool having multiple storage drive arrays; designating an initial available storage capacity in the storage pool; and allocating the remaining storage capacity in the storage pool to distributed spare space, wherein distributed spare space spreads portions of a spare drive across multiple storage drives in an array. The method also includes: monitoring an amount of available storage capacity as data is stored to the storage pool and determining when a threshold of a minimum available storage capacity is reached; and re-allocating one or more distributed spare drives from an array to available storage capacity when the threshold of the minimum available storage capacity is reached.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Ian Boden, Gordon D. Hutchison, Lee J. Sanders
  • Patent number: 10255195
    Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 9, 2019
    Assignee: ARM LIMITED
    Inventors: Michal Karol Bogusz, Quinn Carter, Andrew Brookfield Swaine
  • Patent number: 10255186
    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Purdue Research Foundation
    Inventors: Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
  • Patent number: 10248339
    Abstract: A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory. When the controller detects that a first logical page of the logical pages is a currently-used logical page, it detects whether or not the second logical page which belongs to the last logical page of the first logical page is a currently-used logical page in order to find what is truly the last currently-used logical page.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: April 2, 2019
    Assignee: SILICON MOTION, INC.
    Inventor: Szu-I Yeh
  • Patent number: 10241916
    Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Zvika Greenfield, Zeshan A. Chishti, Israel Diamand
  • Patent number: 10241909
    Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Masahiro Arai, Kazuhisa Fujimoto
  • Patent number: 10242013
    Abstract: A method, computer program product and/or system saves an original logical block in a file system and generates a first heatmap reflecting access operations on the original logical block. After taking of a file system snapshot, and receiving information that the original logical block is going to be revised, a second heatmap is generated, reflecting predicted access operations on the revised logical block. The second heatmap is based, at least in part, on the first heatmap. Selecting a physical storage location for the revised logical block is based on the second heatmap.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sasikanth Eda, Shah M. R. Islam, John T. Olson, Sandeep R. Patil
  • Patent number: 10241676
    Abstract: A hardware-based processing node of an object memory fabric can comprise a memory module storing and managing one or more memory objects within an object-based memory space. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The memory module can provide an interface layer below an application layer of a software stack. The interface layer can comprise one or more storage managers managing hardware of a processor and controlling portions of the object-based memory space visible to a virtual address space and physical address space of the processor. The storage managers can further provide an interface between the object-based memory space and an operating system executed by the processor and an alternate object memory based storage transparent to software using the interface layer.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 26, 2019
    Assignee: Ultrata, LLC
    Inventors: Steven J. Frank, Larry Reback
  • Patent number: 10235083
    Abstract: The disclosed computer-implemented method for efficiently moving data within a filesystem may include (1) partitioning, on a storage device, physical address space of a filesystem into a plurality of logical partitions, (2) allocating, on the storage device, at least one container of data block identifiers representing data blocks for each of the logical partitions, (3) maintaining, on the storage device, a partition map of values identifying the container of data block identifiers, the logical partitions, and at least one offset associated with each of the logical partitions, (4) sending, on the storage device, the data blocks from a source logical partition within the logical partitions to a target logical partition within the logical partitions, and (5) updating, on the storage device, the partition map based on the data blocks sent from the source logical partition to the target logical partition. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: March 19, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Anurag Vora, Brad A Boyer, Madhav Buddhi, Freddy James, Ajay P Salpekar
  • Patent number: 10235049
    Abstract: A management device according to an embodiment manages reading and writing of data, by a processing circuit, from and into a first memory unit and a non-volatile memory unit containing a plurality of pages, and includes a setting storage unit, an access processing circuit, and a management circuit. The setting storage unit stores an access method indicating whether first access processing of writing and reading data into and from data transferred to the first memory unit from the non-volatile memory unit or second access processing of directly writing and reading data into and from data stored in the non-volatile memory unit is executed for each of the pages. The management circuit changes the access method for a third page on which the second access processing is set to be performed to the first access processing when quality of the third page is equal to or lower than a reference value.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Shiyo Yoshimura
  • Patent number: 10229059
    Abstract: Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Ayan Mandal, Eran Shifer, Leon Polishuk
  • Patent number: 10229065
    Abstract: Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 10223271
    Abstract: Provided are an apparatus, computer program product, and method to perform cache operations in a solid state drive. A cache memory determines whether data for a requested storage address in a primary storage namespace received from a host system is stored at an address in the cache memory namespace to which the requested storage address maps according to a cache mapping scheme. Multiple of the storage addresses in the primary storage map to one address in the cache memory namespace. The cache memory returns to the host system the data at the requested address stored in the cache memory namespace in response to determining that the data for the requested storage address is stored in the cache memory namespace.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mariusz Barczak, Piotr Wysocki