Abstract: An apparatus and method for organizing a data array within a cache system to store a plurality of physical pages of data. A single data array is associated with a plurality of tag arrays, each tag array tracking a page size portion of the data array. Indexing into each of the tag arrays is accomplished using the page index from either of the virtual address or the physical address. In addition, selection of indexed tags from the tag arrays is performed by array selection logic which utilizes portions of either of the virtual page number or the physical page number.

Abstract: The state of cached data may be modified without performing a tag comparison. Each cache line includes at least one attribute bit and at least one state bit. A processor issues an instruction requesting modification of the state of all cache lines associated with an attribute specified by the instruction. Qualifying logic modifies the state of a cache line as a function of the attributes stored in the cache line and the attribute specified by the instruction.

Abstract: A system (10) and method for providing simultaneous data reading and writing for a random access memory (18) include storing new data (14) and a corresponding new data address (26), comparing the new data address to a current read address (32), and substituting (38) the new data for the data at the current read address at the output (38) while simultaneously writing the new data into the memory (18). The system and method are particularly suited for application in space-based communication satellites which utilize continuous memory read accesses since the invention provides the functionality of a dual-ported RAM while being implementable with fewer gates and less complex control circuitry to provide reduced power consumption.

Abstract: A paging receiver includes a receiver, a decoder 303, a central processing unit 102, a ROM 104 in which programs to be executed by the CPU and data are stored in a plurality of bank modes, a RAM 105, and a demodulated data outputting apparatus. The decoder includes a bank mode switching register 601 that is used to select a plurality of bank modes. The register stores an initial hardware value and a bank switch value that is used to select one of the plurality of bank modes upon initialization by software, and one of the plurality of bank modes is selected in accordance with the initial hardware value and the bank switch value by the software. When the capacity of the ROM is limited, the capacity of the ROM can be assured sufficiently only by selecting one of the bank modes, and software designing can proceed only after some change of design.

Abstract: An interface between a memory that has "n" address bit inputs and a processor which has "p" address bit outputs (where p<n) and "q" programmable data bit outputs (where q.gtoreq.n-p). The interface includes a logic circuit connected to a byte select bit output, to a memory read-write command bit output and to an appropriately programmed one of the "q" programmable bit outputs of the processor. The logic circuit produces a least significant bit address bit input AI0 defined by the equation AI0=R/W & byte-s OR R/W & I/O0. The interface connects the remaining "p" address bit inputs of the memory succeeding to the "p" address bit outputs of the processor, in order, and connects the remaining "n-p-1" most significant address bit inputs of the memory to the same number of appropriately programmed programmable bit outputs of the processor.

Abstract: A method and apparatus for detecting DRAM symmetry. A memory address including a row address and a column address bit is forced to a known value regardless of the host bit which would otherwise be mapped thereto. If the forced bit is in the column address it should be a bit which is not used by an asymmetric DRAM of the depth in the system to be tested, but would be used in a symmetric DRAM of the same depth. Conversely, if the forced bit is in the row address the bit should be used in the asymmetric case but not in the symmetric case. It is important that regardless of what bit in the memory address is forced, the forced bit should not be used by both cases at the depth tested. A first and second known value, are written respectively to two memory addresses which differ only in the value which would normally be mapped to this forced bit. The forced bit will cause an overwrite if the DRAM is of the type which uses the forced bit in its addressing.

Abstract: A digital signal processor includes first and second counters which increment from each initial address value in first and second address areas synchronous with first and second sampling clock signals, an address generating circuit which generates a first address number in the above first address area according to a counter value in the above first counter and generates a second address number in the above second address area according to a counter value in the above second counter, a data memory which stores information signals supplied synchronous with the above first and second sampling clock signals in the first and second address numbers generated by the above address generating circuit readably and an arithmetic operating circuit which performs arithmetic operation of information signals stored in the above data memory.

Abstract: A configuration management subsystem of a subsystem array system assigns heat producing devices to clusters such that the number of devices activated will not create overheating, regardless of which limited set of clusters is activated. The subsystem receives the dimensions of the disk array, the number of devices, the number of cluster groups and the maximum number of clusters that can be operated substantially simultaneously, and the dimensions of a critical box that defines an arrangement of the devices into cells such that, if a device is assigned to each cell of the critical box and all devices are operated simultaneously, then thermal operating restrictions of the devices will be exceeded. The system first executes simple numbering loop operations to determine, if they exist, dimensions of a building block subarray that meet certain requirements relative to the input parameters.

Abstract: An apparatus for storing selectors directly into segment registers within a single processor cycle. New selectors are stored into addressable segment registers prior to being validated. Old selectors which are shifted into temporary register space prior to being overwritten. If a selector fails validation tests, and requires restoration, the old selector is shifted back into the appropriate segment register thereby restoring the state of the selector.

Abstract: Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

Abstract: A computer system having virtual memory that can be mapped using multiple page sizes onto logically addressable physical memory. An intermediate addressing scheme permits the mapping of several non-contiguous small pages in physical memory onto a bigger sized virtual memory page. Rather than translating a virtual address directly into a physical address, a virtual address is translated into an intermediate address that may or may not be a physical address. If the virtual page is backed by physical memory that is contiguous and aligned on a proper boundary for the page size, then the intermediate address will be the physical address and no second translation is required. If the intermediate address is not a physical address, it is then translated into a physical address. This is the case where a big page in virtual memory is backed by more than one smaller page in physical memory.

Abstract: Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.

Abstract: Method and apparatus for performing bus reflection operation using a data processor (10). The present invention allows a multiplexed peripheral bus master (16) to interface with non-multiplexed peripherals (12, 14) by using a data processor (10) to reflect an address value from the data bus (20) to the address bus (18), or alternately, from the address bus (18) to the data bus (20). In one embodiment, external bus master (16) provides the reflect request signal (30) to data processor (10), and in response, data processor (10) receives the address value provided by external bus master (16) on data bus (20) and drives this same address value on address bus (18) to memories (12, 14). In addition, the present invention allows an external bus master (16) to use the handshake circuitry (50) on data processor (10) to interface with peripheral devices (12,14).

Abstract: A method and apparatus for modifying protective page fault, which executes TLB table walk when protective page fault occurs in order to modify protective page fault. The method includes the following steps: (1) detecting the occurrence of protective page fault; (2) executing protective page fault processing mechanism; (3) executing protective page fault service routine; (4) returning to the address where protective page fault occurs; (5) executing TLB table walk to complete modification for protective page fault; and invalidating the TLB entry for protective fault page at step (2).

Abstract: When a computer system is upgraded, such as by adding a more advanced processor chip and/or a new operating system, a different page size may be employed. The page size is altered for data previously stored in a storage medium such as a hard disk in the computer system, without removing all of the data from the medium and rewriting it. Data is stored in the medium in blocks or sectors which have headers defining the block. Also, tables define memory objects and segments, and locate virtual memory addresses in physical memory. The headers and/or tables can be changed without rewriting all of the data in the sectors or pages in physical memory, so the page size is changed to accommodate the new system components, without excessive burden on system hardware or undue expenditure of time.

Abstract: A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers.

Abstract: A dynamic tag match circuit (10) has exclusive-OR gates (18) each of which receives one bit of an address signal (A) from cache tag RAM, an inverted bit of the address signal (NA) from the cache tag RAM, and one bit of an address signal (B) from an address translator. The exclusive-OR gates (18) are in parallel to each other and output a hit signal which is low only when a match occurs between the two address signals. Additionally, the hit signal is low only when the results of a force miss circuit (14) indicate that a force miss should not occur. The dynamic tag match circuit (10) further has a pull-up circuit (16) for precharging the output of the circuit (16) and for holding the output of the circuit (16) at one of the two logical levels. The force miss circuit (14) advantageously incorporates logic which coordinates the timing of the force miss evaluation with the arrival of the address (A) from the cache tag RAM.

Abstract: A mechanism for distributing interrupts to processors within a multi-processing system including a cache memory corresponding to each processor, a main memory, a bus structure connecting the processors and their associated cache memories with the main memory, and a cache coherency mechanism to maintain data consistency between the cache memories and the main memory. An address within the main memory is assigned to each processor within the system, the assigned address being associated with an interrupt for the processor to which it is assigned. For each processor, a copy of the contents of its assigned address is thereafter read into its corresponding cache memory. Thereafter when a cache coherency operation to update the contents or status of the cache memory address occurs, a comparison is made between the cache memory address presented to the cache memory through the system bus structure and a stored interrupt base address.

Abstract: The present invention relates to computer systems utilizing a TLB with variable sized pages. This invention detects conflicts between address tags stored in the TLB and a prospective address tag. In particular this invention detects conflicts when the prospective tag represents an address space that overlaps, wholly includes or is included in the address space represented by a tag stored in the TLB. By detecting tag conflicts utilizing hardware, a tremendous performance gain is achieved over systems utilizing prior art software systems.

Abstract: A memory access method and apparatus which may access bytes of information from two contiguous memory segment addresses at a time. The amount of information which is accessed at one time is a memory access unit. The number of bytes in a memory segment is also the number of bytes in a memory access unit. The method and apparatus for accessing memory divides each memory segment between separate memories having the same number as the number of bytes in a memory segment. Each of the memories are simultaneously addressed according to a segment address input and an offset input, to thereby enable selected bytes of information stored through two contiguous memory segment addresses to be accessed. Although bytes in two contiguous memory segments may be accessed at a given moment, no more bytes than are contained in a memory access unit are accessed at a given moment.