Abstract: A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus.

Abstract: A memory patching device for a computer system is provided which temporarily changes part of an object program. A patch table containing patch information associated with each data to be patched is stored in storage means. Patch information retriever retrieves patch information associated with an object program from the patch table when the object program is started. Address calculator calculates an absolute address in a main memory of data of the object program to be patched, based on a base address in the main memory at which the object program is loaded, and an offset address contained in the retrieved patch information. A patcher patches data stored at the calculated absolute address of the main memory, based on patch data contained in the retrieved patch information. The patch information retriever, the address calculator, and the patcher constitute a patch library which is contained in the object program.

Abstract: An efficient method for implementing string operations used to process blocks of data within a memory. The registers used to track the memory addresses are updated and committed before the outcome of a read or write address operation is known. In the event an exception occurs, exception handling hardware and microcode is used to restore the state of the registers to the condition they were in prior to the iteration which produced the exception. This reduces the number of microcode instructions required to implement the string operation, producing a faster cycling of the code through multiple iterations. The result is a more optimal code for string operations and a decrease in the time required to carry out the string instruction.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: An apparatus and method for controlling the reconfiguration of the physical storage area in a real storage device employed by an information processing system.The invention includes an address reconfiguration array having a plurality of storage blocks which are each assigned to a virtual computer. Each storage block is composed of a plurality of host real-address entries. Assigned to a storage area in the logical memory of a virtual computer, each host real-address entry includes a validity field containing a validity bit and a host real-address field containing a high-order part of the start address of a real storage segment allocated to the storage area. The invention also includes a selector which receives the identifier of a virtual computer and a logical address from the virtual computer, and makes use of the identifier for choosing a storage block from the address reconfiguration array and a high-order portion of the logical address for selecting a host real-address entry from the chosen storage block.

Abstract: A method and system for supporting discontiguous drive arrangements in a computer system using IDE control parameters having a central processing unit, user interface, short term volatile memory storage, and at least one, to four or more long term static memory storage devices, all of which are connected by a bus to the CPU, is used to provide access to the long term memory storage devices in a manner transparent to both the system and the user.

Abstract: A video driver in a computer system is used to map a large video frame buffer into the logical address space above physical memory while the computer system is operating in WINDOWS STANDARD mode. The requirements of the necessary address space for the frame buffer (i.e., the size of the frame buffer), and the size of physical memory are determined. If there is sufficient address space above physical memory in which to map the frame buffer, the video driver attempts to map the frame buffer there in that address space. The desired physical and linear addresses for the frame buffer are determined. If the video driver detects that MICROSOFT WINDOWS is operating in standard mode, it searches memory to find the page directory that MICROSOFT WINDOWS created. Once the page directory is found, the driver creates a new page table to map the frame buffer into the desired linear address range and adds a new entry to the existing page directory to point to the new page table.

Abstract: This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values.

Abstract: A circuit is provided for incrementing a current address of a circular buffer in an electronic memory by an increment to produce a next address including: an adder circuit for adding the current address to the increment and producing a first provisional next address; a circuit which causes the next address to be a base address plus an overshoot when the first provisional next address passes a limit address by a number equal to the overshoot, wherein for the calculation of the next address, there is provided an adder circuit including three adders receiving the current address, the increment and the limit address and producing a first and a second provisional next address and the difference between the first provisional next address and the limit address; and a selection circuit for selecting as the next address one of the two provisional next addresses, the selection being made upon the polarity of the difference between the first provisional next address and the limit address.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: The present invention discloses processor elements interconnected via a network in a parallel computer.

Abstract: An additional function is provided to an otherwise conventional operating system for superimposing visibility windows on the GDT and the LDTs for the purpose of memory protection. In a first embodiment, the operating system is also provided with a first additional control logic for selectively invoking the visibility window function to impose visibility windows of different window sizes for different tasks. In a second embodiment, the operating system is provided with a second additional control logic for selectively invoking the visibility window function to impose visibility windows of different window sizes for different operating system functions. In a third embodiment, the operating system is provided with the first as well as the second additional control logic.

Abstract: A method and apparatus to share virtual memory translations in a computer is described. The apparatus includes an operating system that runs in conjunction with a central processing unit. The operating system is programmed to include an address identification routine to identify distinct virtual memory translation entries, associated with a plurality of distinct processes running on the computer, that map to one or more common physical memory page addresses. The operating system also includes a mask assignment routine to assign a first mask value to the distinct virtual memory translation entries, and a write routine to write, to a translation-lookaside buffer or a page table, the distinct virtual memory translation entries as a single address associated with the first mask value. A comparison mechanism is used to compare a second mask value of a translation-request virtual memory translation value to the first mask value to determine whether the second mask value corresponds to said first mask value.

Abstract: A lossless data compression system and method compresses a set of M data words stored in a computer memory. A first table stores data representing last occurrence positions among those of the M data words already processed for all distinct word values. A second table stores for each data word an entry indicating the position, if any, of a most recent prior occurrence of another data word with the same word value. A dictionary index indicates how many distinct data word values have been encountered during processing of M data words.

Abstract: A data storage system includes a data storage medium, such as a magnetic tape, that has a first control data storing area or drive partition that is addressable only by a peripheral drive mounting the medium and a plurality of other addressable data storing partitions for storing data. A volume table of contents may be stored in one of the addressable partitions. A tachometer measures and indicates physical locations on the storage medium. Each of the partitions have an extent on the storage medium indicated by said physical locations. The control data in the drive partition includes directories of medium control blocks, such as tape marks, defect marks and the like; directory of all addressable partitions including the physical locations at the beginning of each partitions and other medium physical and logical parameter data. A so-called mount-demount medium control block in the drive partition indicates a demount status that shows all data stored in the drive partition is valid.

Abstract: A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address determined from the relative address is also generated. The actual base address determination takes longer to generate than the predicted base address determination, and therefore the predicted base address is used to select a base address as long as the prediction is correct. Circuitry exists to compare the predicted base address with the actual base address, and if not equal, the predicted base address will be nullified, and the actual base address will be used. Prediction modes are dependent on whether the relative address indicates an instruction fetch or an operand fetch. Where the relative address indicates an instruction fetch, the prediction will be based on the last base address used, on the assumption that instructions will be contiguous in a single block of memory.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

Abstract: A decoder uses look-up table memory for variable-length coding (such as Huffman coding) that comprises concatenated variable-length codes, most species of which codes can each be analyzed as being composed of a pointer subcode of variable bit-length and a target subcode of fixed bit-length, the target subcodes being relatively efficiently encoded and the pointer subcodes being relatively inefficiently encoded. The memory stores not only decoding results, but the bit-lengths of the codes generating those results. The bit-lengths of the concatenated codes are accumulated and the accumulation result in modular arithmetic is supplied to as shift control signal to a data shifter. The data shifter positions each successive one of the concatenated codes within a window so the leadmost bit of the code is positioned at the edge of the window. The pointer subcodes are decoded, applied to address lines of the memory, and used to select target subcodes to an address decoder.

Abstract: The present invention is to improve the processing capability of a micro processor by speeding up a read operation of program memory stored in a ROM. The present invention comprises a first ROM for storing program data corresponding to even-numbered addresses and a second ROM for storing program data corresponding to odd-numbered addresses. It further comprises an address generator circuit for adding +1 to an address indicated by A1 - An when a least significant address bit A0 is 1. Hereby, when a present read operation is done for an odd-numbered address, an even-numbered address next to the foregoing odd-numbered address is simultaneously read to speed up read operation from a ROM.

Abstract: In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass memory), the processors are organized into clusters, each having a plurality of processors and a common secondary cache. Each cluster is assigned a two-bit cluster number. Intermediate a primary cache in each processor and the secondary cache in the cluster, an address translator is provided for effecting transformation between internal memory space addresses and external memory space addresses. The external memory space is divided into areas private to each cluster and shared by all the processors. An internal address indicator bit, in conjunction with the cluster number from a requesting processor primary cache, is employed to set up the transformation either to the private external space of that cluster or the shared external space.