Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.

Abstract: An image sensor includes a plurality of filters, an air spacer formed between the plurality of filters, and a protection layer including a first part formed on the plurality of filters and a second part formed on the air spacer. The second part of the protection layer may have a convex lens shape that protrudes over the plurality of filters.

Abstract: Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

Abstract: An integrated circuit system having: (A) a semiconductor chip with a signal strip conductor disposed on an upper surface of the chip; an active semiconductor device disposed of the upper surface of the chip electrically connected to the signal strip conductor; and a first ground plane conductor disposed on a bottom surface of the chip disposed under the signal strip conductor; and (B) a support structure having: a second ground plane disposed over, and separated from, the signal strip conductor by a dielectric region between the second ground plane and the signal strip conductor on the chip; a signal contact disposed on the bottom surface of the support structure displaced, electrically insulated, from the second ground plane conductor, and electrically connected to a portion of the signal strip conductor. The signal strip conductor, the first ground plane conductor, and the second ground plane conductor provide a stripline microwave transmission line.

Abstract: A photodetection device of the present invention includes a semiconductor substrate which is defined such that a first light-receiving portion and a second light-receiving portion are spaced from one another, and an optical filter which is formed on the semiconductor substrate, and includes a first filter which is disposed so as to cover the first light-receiving portion, to selectively allow an optic element in a first wavelength band to transmit through, and a second filter which is disposed so as to cover the second light-receiving portion, to selectively allow an optic element in a second wavelength band different from the first wavelength band, to transmit through, and the optical filter has a filter laminated structure which is defined such that edge portions of the first filter and the second filter overlap one another on a boundary region between the first light-receiving portion and the second light-receiving portion.

Abstract: A method of manufacturing a display device is provided which uses a sacrificial layer interposed between a carrier and a display device substrate.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Abstract: A solid-state image sensing device is provided including a first semi-conducting layer of first conductivity, a second semi-conducting layer of first conductivity disposed on the first semi-conducting layer, a semiconductor region of second conductivity different from the first conductivity disposed in the second semi-conducting layer, a deep trench configured to isolate a plurality of neighboring pixels from each other, and an electrode implanted into the deep trench, where the semiconductor region of second conductivity, the second semi-conducting layer, and the first semi-conducting layer are disposed in that order from a proximal side to a distal side, the second semi-conducting layer is split by the deep trench into sections that correspond to the pixels, an impurity concentration of first conductivity of the first semi-conducting layer is higher than an impurity concentration of first conductivity of the second semi-conducting layer, and the deep trench contacts the first semi-conducting layer.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.

Abstract: A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Abstract: A light-emitting structure comprises a semiconductor light-emitting element which includes a first connection point and a second connection point. The light-emitting structure further includes a first electrode electrically connected to the first connection point, and a second electrode electrically connected the second connection point. The first electrode and the second electrode can form a concave on which the semiconductor light-emitting element is located.

Abstract: A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.

Abstract: In a display portion of a liquid crystal display device, the dead space corresponding to a unit pixel is reduced while the aperture ratio of the unit pixel is increased. One amplifier circuit portion is shared by a plurality of unit pixels, so that the area of the amplifier circuit portion corresponding to the unit pixel is reduced and the aperture ratio of the unit pixel is increased. In addition, when the amplifier circuit portion is shared by a larger number of unit pixels, a photosensor circuit corresponding to the unit pixel can be prevented from increasing in area even with an increase in photosensitivity. Furthermore, an increase in the aperture ratio of the unit pixel results in a reduction in the power consumption of a backlight in a liquid crystal display device.

Abstract: A microelectromechanical systems (MEMS) die includes a substrate having a first substrate layer, a second substrate layer, and an insulator layer interposed between the first and second substrate layers. A structure is formed in the first substrate layer and includes a platform upon which a MEMS device resides. Fabrication methodology entails forming the MEMS device on a front side of the first substrate layer of the substrate, forming openings extending through the second substrate layer from a back side of the second substrate layer to the insulator layer, and forming a trench in the first substrate layer extending from the front side to the insulator layer. The trench is laterally offset from the openings. The trench surrounds the MEMS device to produce the structure in the first substrate layer on which the MEMS device resides. The insulator layer is removed underlying the structure to suspend the structure.

Abstract: A method of forming infra red detector arrays is described, starting with the manufacture of a wafer. The wafer is formed from a GaAs or GaAs/Si substrate having CMT deposited thereon by MOVPE. The CMT deposited comprises a number of layers of differing composition, the composition being controlled during the MOVPE process and being dependent on the thickness of the layer deposited. Other layers are positioned between the active CMT layers and the substrate. A CdTe buffer layer aids the deposition of the CMT on the substrate and an etch stop layer is also provided. Once the wafer is formed, the buffer layer, the etch stop layer and all intervening layers are etched away leaving a wafer suitable for further processing into an infra red detector.

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract: Provided are a semiconductor device in which a solid-state image sensing element having a backside-illuminated structure and capacitor elements storing therein some of the charges supplied from light receiving elements has further improved reliability and a manufacturing method thereof. In the solid-state image sensing element of the semiconductor device, first and second substrates are joined together at a junction surface. The first substrate is formed with photodiodes. The second substrate is formed with the capacitor elements. The photodiodes and the capacitor elements are placed to be opposed to each other. In the first substrate, first coupling portions for coupling to the second substrate are placed. In the second substrate, second coupling portions for coupling to the first substrate are placed. A first gap portion between the first coupling portions and a second gap portion between the second coupling portions are placed to overlap a first light blocking film.

Abstract: An integrated MEMS system in which CMOS and MEMS devices are provided to form an integrated CMOS-MEMS system. The system can include a silicon substrate layer, a CMOS layer, MEMS and CMOS devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, one which any number of CMOS MEMS devices can be configured.