Patents Examined by Thanh Y. Tran
  • Patent number: 11367759
    Abstract: An electroluminescence display device comprising a through-hole in a display area is discussed. The electroluminescence display device according to one embodiment of the present disclosure comprises a substrate having a display area and a non-display area arranged near the display area; a light emitting diode in the display area; an encapsulation layer on the light emitting diode; a through-hole arranged inside the display area to penetrate the substrate; an inner dam surrounding the through-hole; a trench arranged between the inner dam and the through-hole; and an etch-stopper arranged between the trench and the through-hole on the an insulating layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 21, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: HaeRi Huh
  • Patent number: 11367712
    Abstract: A semiconductor device according to the present embodiment includes a first chip and a second chip. A first pad is disposed so as to be exposed from a first region on a first surface. A first mark is provided by a first pattern and is disposed so as to be exposed from a second region. The second chip includes a second substrate, a second wire, a second pad, and a second mark. The second wire is disposed on the second substrate. The second pad is disposed so as to be exposed from a third region on a second surface, and is electrically connected to the second wire and the first pad. The second mark is provided by a second pattern corresponding to the first pattern, is disposed so as to be exposed from a fourth region, and has a thinner thickness than the second pad.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventor: Takashi Watanabe
  • Patent number: 11362066
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, a second semiconductor die, an insulating layer, and a first dual-damascene connector electrically connected to the first semiconductor die. The first semiconductor die includes a first bonding surface including a die attaching region and a peripheral region connected to the die attaching region. The second semiconductor die is electrically connected to the first semiconductor die, and a second bonding surface of the second semiconductor die is bonded to the first bonding surface in the die attaching region. The insulating layer disposed on the first bonding surface in the peripheral region extends along sidewalls of the second semiconductor die. The first dual-damascene connector includes a first portion disposed on the insulating layer, and a second portion penetrating through the insulating layer and landing on the first bonding surface in the peripheral region.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11353604
    Abstract: Disclosed herein is a method for making an apparatus suitable for detecting X-ray, the method comprising: obtaining a wafer and a substrate; wherein the substrate comprises an X-ray absorption layer comprising a first plurality of electrical contacts; wherein the wafer has multiple dies and comprises an electronic layer comprising a second plurality of electrical contacts and an electronic system configured to process or interpret signals generated by X-ray photons incident on the X-ray absorption layer; aligning the first plurality of electrical contacts to the second plurality of electrical contacts; mounting the wafer to the substrate such that the first plurality of electrical contacts are electrically connected to the second plurality of electrical contacts; wherein the substrate further comprises a transmission line electrically bridging at least some of the dies; wherein the second plurality of electrical contacts are configured to feed the signals to the electronic system.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 7, 2022
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 11349032
    Abstract: A semiconductor device having favorable characteristics is provided. A semiconductor device having stable electrical characteristics is provided. An island-shaped insulating layer containing an oxide is provided in contact with a bottom surface of a semiconductor layer containing a metal oxide that exhibits semiconductor characteristics. The insulating layer containing an oxide is provided in contact with a portion of the semiconductor layer to be a channel formation region and is not provided under portions to be low-resistance regions.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 31, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 11348910
    Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 31, 2022
    Inventors: Chanho Kim, Kyunghwa Yun, Daeseok Byeon
  • Patent number: 11335666
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11335639
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 11335743
    Abstract: An electroluminescence display device comprising a through-hole in a display area is discussed. The electroluminescence display device according to one embodiment of the present disclosure comprises a substrate having a display area and a non-display area arranged near the display area; a light emitting diode in the display area; an encapsulation layer on the light emitting diode; a through-hole arranged inside the display area to penetrate the substrate; an inner dam surrounding the through-hole; a trench arranged between the inner dam and the through-hole; and an etch-stopper arranged between the trench and the through-hole on the an insulating layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: May 17, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: HaeRi Huh
  • Patent number: 11335782
    Abstract: [Solving Means] An oxide semiconductor thin film according to an embodiment of the present invention includes: an oxide semiconductor that mainly contains In, Sn, and Ge. An atom ratio of Ge/(In+Sn+Ge) is 0.07 or more and 0.40 or less. As a result, it is possible to achieve transistor characteristics with a mobility of 10 cm2/Vs or more.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 17, 2022
    Assignee: ULVAC, INC.
    Inventors: Taku Hanna, Motoshi Kobayashi, Jungo Onoda
  • Patent number: 11328955
    Abstract: A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Bernhard Goller
  • Patent number: 11328984
    Abstract: Multi-die integrated circuit packages and methods of manufacturing the same are disclosed. An example integrated circuit package includes a first leadframe, a first die on a first side of the first leadframe, and a second die on a second side of the first leadframe opposite the first side. The example integrated circuit package further includes external second leadframe separate from the first leadframe.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: You Chye How, Huay Yann Tay, Franklin Santos Marcelino
  • Patent number: 11322498
    Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 11322483
    Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 3, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Ken Oowada, Mitsuteru Mushiga
  • Patent number: 11315856
    Abstract: In a general aspect, a method can include coupling a semiconductor component to a leadframe. The leadframe can include a socket member having a first end portion and a second end portion. The socket member can further include an opening disposed between the first end portion and the second end portion. The opening of the socket member can be configured to receive a solderless pin. The method can also include encapsulating, in a molding compound, at least a portion of the leadframe and at least a portion of the semiconductor component such that the opening of the socket member is exposed through the molding compound.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 26, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tiburcio Maldo, Keunhyuk Lee
  • Patent number: 11309387
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11296062
    Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo
  • Patent number: 11270975
    Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Po-Yao Chuang, Shuo-Mao Chen
  • Patent number: 11270947
    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Shawna Liff, Johanna Swan, Gerald Pasdast
  • Patent number: 11270968
    Abstract: The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 8, 2022
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masaru Hashino, Ying Ying Lim, Hiroshi Nakagawa, Masahiro Aoyagi, Katsuya Kikuchi