Patents Examined by Thanh Y. Tran
  • Patent number: 11031285
    Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 8, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 11024600
    Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a programmable logic device and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 1, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Weihua Cheng
  • Patent number: 11018141
    Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 11018081
    Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng, Techi Wong
  • Patent number: 11004732
    Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively; forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region; forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including first colloid; and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-ki Min, Koung-min Ryu, Sung-soo Kim, Sang-koo Kang
  • Patent number: 10998442
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Patent number: 10991674
    Abstract: Provided is an electronic assembly including (a) an interconnect carrier having an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; (b) a first integrated circuit chip mounted at a first side of the interconnect carrier; (c) a second integrated circuit chip mounted at a second side of the interconnect carrier opposite to the first side; and (d) an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip. The electric interconnection structure extends around the insulating core and includes at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided. Further, there is provided an electronic system comprising such an electronic assembly.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 27, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Gerald Weis
  • Patent number: 10991713
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Keisuke Nakatsuka, Fumitaka Arai, Shinya Arai, Yasuhiro Uchiyama
  • Patent number: 10991811
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10985345
    Abstract: An organic light emitting diode display device includes a display panel including an array substrate displaying an image, a face sealing adhesive layer attached to the array substrate, a side sealing layer covering a side surface of the array substrate, and a protecting substrate attached to the array substrate through the face sealing adhesive layer; and a printed circuit board attached to the protecting substrate.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyeon-Yong Eom, Chul Park, Seung-Hwan Lee, Chan-Hee Park
  • Patent number: 10985253
    Abstract: The present invention relates, for example, to a semiconductor structure containing multiple parallel channels in which several parallel conductive channels are formed within the semiconductor structure. Electric contact or electrostatic control over all these channels is done by three-dimensional electrode structures. The multiple channel structure with three-dimensional electrodes can be applied to semiconductors devices such as field effect transistors, diodes, and other similar electronic or quantum-effect devices. This structure is practical for materials where multiple parallel conduction channels can be formed, such as in III-V semiconductors. Ill-Nitride semiconductors with such structures are described which can lead to increased power density, reduced on-resistance and improved device performance, in addition to reducing dynamic on-resistance, and improving the stability of their threshold voltage and reliability.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 20, 2021
    Assignee: ECOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)
    Inventors: Elison de Nazareth Matioli, Jun Ma
  • Patent number: 10978384
    Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-hyung Kim, Chan-Ho Lee
  • Patent number: 10971645
    Abstract: Example embodiments relate to controlling detection time in photodetectors. An example embodiment includes a device. The device includes a substrate. The device also includes a photodetector coupled to the substrate. The photodetector is arranged to detect light emitted from a light source that irradiates a top surface of the device. A depth of the substrate is at most 100 times a diffusion length of a minority carrier within the substrate so as to mitigate dark current arising from minority carriers photoexcited in the substrate based on the light emitted from the light source.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 6, 2021
    Assignee: Waymo LLC
    Inventors: Caner Onal, Simon Verghese, Pierre-Yves Droz
  • Patent number: 10971554
    Abstract: An organic light-emitting device and display apparatus, the device including a first electrode; a second electrode facing the first electrode; an emission layer between the first and second electrode; a hole control layer between the first electrode and the emission layer; and an electron control layer between the emission layer and the second electrode, wherein the emission layer includes a plurality of sub-emission layers to emit light having different wavelengths, at least portions of the plurality of sub-emission layers do not overlap one another, the plurality of sub-emission layers include: a first sub-emission layer including a first color light-emitting dopant, and a second sub-emission layer including a second color light-emitting dopant, the first and second sub-emission layers each include a hole-transporting and electron-transporting host which form an exciplex, and a triplet energy of the exciplex is equal to or greater than triplet energies of the first and second color light-emitting dopant.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: April 6, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hajin Song, Jihwan Yoon, Sangwoo Lee, Sangwoo Pyo
  • Patent number: 10964883
    Abstract: According to one embodiment, a magnetic storage device includes a magnetoresistive effect element. The magnetoresistive effect element including: a first ferromagnetic layer; a second ferromagnetic layer; a first non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer; a second non-magnetic layer at an opposite side of the first non-magnetic layer relative to the first ferromagnetic layer; and a third non-magnetic layer at an opposite side of the first ferromagnetic layer relative to the second non-magnetic layer. The second non-magnetic layer including rare-earth oxide, and the third non-magnetic layer including ruthenium (Ru) or molybdenum (Mo).
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Watanabe, Toshihiko Nagase
  • Patent number: 10962178
    Abstract: Disclosed are a device and a method for pressure-molding an anti-overheating CSP fluorescent membrane. The device comprises a frame, a mould pressing device, a force measuring device, a control device and a feeding device; and the mould pressing device comprises an upper pressing mould, an upper clamp, a lower pressing mould, a guide post, an elastic supporting structure, and a lower clamp. As the stage of pressing the elastic supporting structure is added to the course of pressure molding, a mould clamping force of the pressure molding increases in a relatively steady way, and a force impact of a mould clamping device is reduced, thereby easily determining an initial point for maintain temperature of the pressure molding.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 30, 2021
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Zongtao Li, Qinghong Lin, Yong Tang, Shudong Yu, Huiyu Wang, Guanwei Liang, Longsheng Lu
  • Patent number: 10957790
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 23, 2021
    Assignee: NXP USA, Inc.
    Inventors: Bruce McRae Green, Darrell Glenn Hill, Karen Elizabeth Moore, Jenn-Hwa Huang, Yuanzheng Yue, James Allen Teplik, Lawrence Scott Klingbeil
  • Patent number: 10950564
    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10943886
    Abstract: Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 9, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Eiji Kurose
  • Patent number: 10937721
    Abstract: A semiconductor structure includes a first die, a molding at least partially surrounding the first die, a via extended through the molding, a second die disposed over the molding, a connector dispose between the second die and the via, and an underfill at least partially surrounding the connector. The first die includes a first surface and a second surface opposite to the first surface. The second die includes a third surface facing the first die, a fourth surface opposite to the third surface, and a sidewall between the third surface and the fourth surface. The connector is in contact with the third surface of the second die and the via. The second die is electrically connected to the via. The underfill covers a portion of the sidewall of the second die and a portion of the second surface of the first die.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien Hsun Lee