Patents Examined by Thanh Y. Tran
  • Patent number: 10431691
    Abstract: The present application discloses a thin film transistor, a method for manufacturing a thin film transistor and a liquid crystal display panel, and relates to a display technology field. The thin film transistor includes a substrate, a gate electrode layer and an insulating layer, the gate electrode layer is formed on the substrate, the insulating layer is covered on the gate layer; a semiconductor layer is formed on the insulating layer; a conductor layer is formed on the semiconductor layer; an insulating spacer layer is formed on the insulating layer; a source-drain electrode layer is formed on the conductor layer and the insulating spacer layer; a passivation layer formed on the source-drain electrode layer and the semiconductor layer; wherein the insulating spacer layer is located between the source-drain electrode layer and the semiconductor layer to solve the leakage current too large problem of the thin film transistor.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 1, 2019
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Songshan Li
  • Patent number: 10416225
    Abstract: A detection method for an LED chip comprising the following steps: providing a container with a solvent therein, and putting the LED chips in the container to mix the LED chips with the solvent; providing a base with a circuit therein, the base forms a plurality of receiving holes, a bottom of each receiving holes have an N electrode and a P electrode coupled with the circuit; transferring the solvent and the LED chip mixed in the solvent on the base; detecting the LED chip received in the receiving holes; providing a carrier film and classifying the LED chips on the carrier film.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: September 17, 2019
    Assignee: ADVANCED OPTOELECTRONICS TECHNOLOGY INC.
    Inventors: Po-Min Tu, Tzu-Chien Hung, Chia-Hui Shen, Chien-Shiang Huang, Chien-Chung Peng, Ya-Wen Lin, Ching-Hsueh Chiu
  • Patent number: 10403747
    Abstract: A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 3, 2019
    Assignee: Nexperia B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Johannes Josephus Theodorus Marinus Donkers, Jan Sonsky, Jeroen Antoon Croon
  • Patent number: 10396101
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji Hun Lim, Joon Seok Park
  • Patent number: 10396186
    Abstract: A thin film transistor, a method for fabricating the same, a display panel and a display device are disclosed. The method includes forming an active layer on a substrate; forming an insulating layer on the active layer and an exposed surface of the substrate; forming a first conductive layer on the insulating layer; patterning the first conductive layer and the insulating layer to form a first stack on the active layer, wherein the first stack includes a first portion of the first conductive layer and a first portion of the insulating layer, the first stack acts as a gate stack and the active layer includes a channel region below the gate stack and a source region and a drain region at two sides of the channel region; and performing plasma treatment on the first conductive layer, the source region and the drain region, to improve conductivity.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 27, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiangbo Chen, Quanhu Li, Jingang Fang
  • Patent number: 10388686
    Abstract: A image sensor includes a semiconductor substrate with a photosensitive region. Metallization layers are stacked over the semiconductor substrate. Each metallization layer includes an etch stop layer and a dielectric layer on the etch stop layer. At least one metallization layer includes one or more microlenses positioned over the photosensitive region. The one or more microlenses are integrally formed by the etch stop layer.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 20, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Flavien Hirigoyen
  • Patent number: 10388702
    Abstract: An organic light emitting display device includes a substrate; first and second organic light emitting diodes laterally shifted with respect to each other on the substrate; an encapsulation layer covering the first and second organic light emitting diodes, the encapsulation layer including a plurality of layers; and a first color filter and a second color filter each within the plurality of layers, the first color filter and the second color filter being respectively disposed over respective ones of the first and second organic light emitting diodes at respectively different heights from the substrate.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: August 20, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Dongyoung Kim, YongBaek Lee, Ho-Jin Kim, Goeun Jung
  • Patent number: 10388531
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 10388643
    Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 20, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Ju Hoon Yoon, Seong Min Seo, Glenn Rinne, Choon Heung Lee
  • Patent number: 10381265
    Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-ki Min, Koung-min Ryu, Sung-soo Kim, Sang-koo Kang
  • Patent number: 10378124
    Abstract: A device includes a semiconductor substrate containing gallium nitride and having a crystal face inclined from 0.05° to 15° inclusive with respect to the c-plane. The semiconductor substrate includes an irregular portion on the crystal face, and the contact angle of pure water having a specific resistance of 18 M?·cm or more on the surface of the irregular portion is 10° or less.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 13, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masaki Fujikane
  • Patent number: 10381297
    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Jack E. Murray
  • Patent number: 10374059
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10367051
    Abstract: An active-matrix display device includes: a pixel matrix that includes a plurality of pixel cells arranged in rows and columns; a first global power supply wire that is disposed for each of the columns in the pixel matrix and connected to each of the plurality of pixel cells in the column; and a second global power supply wire that is disposed for each of the columns in the pixel matrix and connected to each of the plurality of pixel cells in the column. Each of the plurality of pixel cells includes a local power supply wire that is connected to the first global power supply wire, and the local power supply wire does not overlap the second global power supply wire in a plan view of the pixel matrix.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 30, 2019
    Assignee: JOLED INC.
    Inventor: Kenji Kokuda
  • Patent number: 10367059
    Abstract: A method of manufacturing a semiconductor structure includes the following steps. A first raised portion is formed on a semiconductor substrate. The height of the first raised portion is reduced, and a dielectric material is formed over the first raised portion. The dielectric material is annealed such that the first raised portion is tilted.
    Type: Grant
    Filed: September 9, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cong-Min Fang, Kang-Min Kuo, Shi-Min Wu
  • Patent number: 10361111
    Abstract: Provided is a plasma processing apparatus which comprises a chamber, a stage configured to set a holding sheet and a substrate held thereon, a securing mechanism configured to secure the holding sheet on the stage, a plasma generator including a first electrode and a first high-frequency power supply, and a determiner for determining a contact status between the holding sheet and the stage, wherein a gas through-hole is arranged on a surface of the stage in an annular region defined between an inner edge of a frame set on the stage and an outer edge of the substrate, and wherein the determiner is configured to determine the contact status in accordance with a pressure of a gas in the gas introduction conduit and/or a regulation data for regulating the pressure of the gas, the gas being introduced between the stage and the holding sheet from the gas through-hole.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Takahiro Miyai
  • Patent number: 10361337
    Abstract: Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, method of manufacturing a micro-light emitting diode (LED) display panel includes positioning a display backplane substrate in a tank or container, the display backplane substrate having microgrooves therein. The method also includes adding a fluid to the tank or container, the fluid including a suspension of light-emitting diode (LED) pixel elements therein. The method also includes moving the fluid over the display backplane substrate. The method also includes assembling LED pixel elements from the fluid into corresponding ones of the microgrooves.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Anup Pancholi, Ali Khakifirooz
  • Patent number: 10354966
    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10340465
    Abstract: An embodiment relates to a composition including at least two powders. The powders are selected from the group including a powder including a p-doped perovskite; a powder including an n-doped perovskite; and a powder including an undoped perovskite. A method for producing the composition, a method for producing a detector using the composition, and a detector, in particular an X-ray detector, produced thereby are also disclosed.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 2, 2019
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Andreas Kanitz, Oliver Schmidt, Sandro Francesco Tedde
  • Patent number: 10332739
    Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation, the method includes providing a substrate comprising an epitaxial layer into a transfer chamber, wherein the transfer chamber has an ultraviolet (UV) lamp module disposed adjacent to a top ceiling of the transfer chamber, flowing an oxygen-containing gas into the transfer chamber through a gas line of the transfer chamber, flowing a non-reactive gas into the transfer chamber through the gas line of the transfer chamber, activating the UV lamp module to oxidize residues or species on a surface of the substrate to form an outgassing barrier layer on the surface of the substrate, ceasing the flow of the oxygen-containing gas and the nitrogen-containing gas into the transfer chamber, pumping the transfer chamber, and deactivating the UV lamp module.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 25, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao, Hua Chung, Schubert S. Chu