Patents Examined by Thao H Bui
  • Patent number: 10002665
    Abstract: Subject matter provided may relate to devices, such as conducting elements, which operate to place correlated electron switch elements into first and second impedance states. In embodiments, conducting elements are maintained to be at least partially closed continuously during first and second phases of coupling the CES elements between a common source voltage and a corresponding bitline.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 19, 2018
    Assignee: ARM Ltd.
    Inventors: Mudit Bhargava, Piyush Agarwal, Akshay Kumar, Glen Arnold Rosendale
  • Patent number: 9953943
    Abstract: A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One or more of the first and second ranks may be configured to output any one of an even-numbered byte and an odd-numbered byte through an input/output stage at a timing earlier than the other one, according to a read command.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: April 24, 2018
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Kyung Whan Kim
  • Patent number: 9875807
    Abstract: A semiconductor memory apparatus may include a data conversion control block configured to control the number of pipe input control signals and the number of pipe output control signals which are enabled, in response to a training control signal. The semiconductor memory apparatus may also include a data conversion block configured to receive parallel data and output serial data, in response to the pipe input control signals and the pipe output control signals.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 23, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 9870826
    Abstract: A memory apparatus and a data access method thereof are provided. The memory apparatus includes a first memory unit and a second memory unit, wherein an access speed of the second memory unit is higher than an access speed of the first memory unit. The method includes: receiving write data and a corresponding write address; comparing the write data with data corresponding to the write address in the second memory unit, so as to determine whether to write the write data into a current physical memory page of the first memory unit and into the second memory unit; after a data writing operation is executed, executing a data arranging operation on the current physical memory page according to the data in the second memory unit when the current physical memory page is full; and when a read command is received, reading the corresponding data in the second memory unit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 16, 2018
    Assignee: Nuvoton Technology Corporation
    Inventors: Chang-Hong Lin, Chun-Hao Huang, Chieh-Sheng Tu
  • Patent number: 9847134
    Abstract: A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: December 19, 2017
    Assignee: Silicon Motion, Inc.
    Inventor: Yi-Hua Pao
  • Patent number: 9804856
    Abstract: A method of operating a clock frequency detected control I/O buffer enable circuitry and/or features of saving power. In illustrative implementations, the method may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 31, 2017
    Assignee: GSI Technology, Inc.
    Inventors: Young-Nam Oh, Soon Kyu Park, Jae Hyeong Kim
  • Patent number: 9799399
    Abstract: A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the plurality of memory chips may include a plurality of nonvolatile memory cell array layers stacked on a substrate in a three dimensional structure. The module controller may control operations of the plurality of memory chips. The module controller may operate each of the plurality of nonvolatile memory cell array layers included in each of the plurality of memory chips in one of a memory mode, in which a corresponding nonvolatile memory cell array layer is used as a working memory area that temporarily stores data for an operation of the nonvolatile memory module, and a storage mode, in which the corresponding nonvolatile memory cell array layer is used as a storage area that preserves data.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronic Co., Ltd.
    Inventor: Kwang-Jin Lee
  • Patent number: 9799393
    Abstract: A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 24, 2017
    Inventors: Hema Ramamurthy, Sanjay Parihar, Jongsin Yun
  • Patent number: 9747967
    Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 29, 2017
    Inventors: Helia Naeimi, Shih-Lien L. Lu, Shigeki Tomishima
  • Patent number: 9728267
    Abstract: A memory device has first and second strings of memory cells coupled to a data line. The first string is for storing a first bit having a first bit significance, and the second string is for storing a second bit having a second bit significance different than the first bit significance. A first resistor is coupled in series with the first string. A second resistor is coupled in series with the second string. The memory device is configured to set the first resistor to a first resistance based on the first bit significance and the second resistor to a second resistance based on the second bit significance so that the second resistance is different than the first resistance. The memory device is configured to compare a first bit of input data to the first bit and to compare a second bit of the input data to the second bit.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: August 8, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 9711192
    Abstract: A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Ran Kim, Tae-Young Oh, Seong-Jin Jang
  • Patent number: 9697890
    Abstract: An interface circuit is provided. A NMOS transistor is coupled between a first bit line and a ground. A logic gate is coupled between a gate of the NMOS transistor and a second bit line. A keeper controls a voltage level of the second bit line according to a reference voltage. A tracking circuit includes a plurality of reference bit cells and a pull-up device coupled to a reference bit line. Each reference bit cell is coupled to a read word line. When a bit cell coupled to the second bit line is accessed by a specific read word line, the reference bit cell coupled to the specific read word line drains a current from the pull-up device. The tracking circuit provides the reference voltage according to the current.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 4, 2017
    Inventor: Bing Wang
  • Patent number: 9680460
    Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: June 13, 2017
    Assignee: SK Hynix Inc.
    Inventor: Chun-Seok Jeong
  • Patent number: 9589644
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 9496878
    Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: November 15, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Joo-Hwan Cho, Kwang-Jin Na, Kwan-Dong Kim
  • Patent number: 9473171
    Abstract: Provided is a data encoding method such that memory cells storing the data form a biased threshold voltage distribution. The data encoding method may include receiving N bits of first data, and converting the first data into M bits of second data, wherein the proportion of a first value in the second data is higher than the proportion of a second value.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Myeong Woon Jeon
  • Patent number: 9443844
    Abstract: A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: September 13, 2016
    Inventor: Yasuhiko Takemura
  • Patent number: 9418001
    Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 16, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
  • Patent number: 9349450
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 24, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 9330776
    Abstract: A high voltage step regulator, such as would be used to provide a regulated low voltage (on the order of a few volts) from a high voltage external supply (e.g. 12V), is presented. To protect the output transistor, through which the output is provided from the input, from breakdown, a depletion type device is connected between the supply and the output transistor. The control gate of the depletion device is then connected to the output level of the regulator. This reduces the voltage drop across the output transistor, helping to avoid violating design rules (EDR) on how great a voltage differential can be placed across the output transistor. Examples of applications for such a circuit are for various operating voltages on a non-volatile memory chip operating with a high voltage power supply.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 3, 2016
    Assignee: SanDISK Technologies Inc.
    Inventors: Jonathan Huynh, Jongmin Park, Trung Pham