Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer, a second terminal having a second raised semiconductor layer, and a base layer positioned laterally between the first raised semiconductor layer and the second raised semiconductor layer. The structure further includes a spacer positioned laterally positioned between the first raised semiconductor layer and the base layer. The spacer includes a dielectric material and an airgap surrounded by the dielectric material.

Abstract: A display substrate is disclosed. The disclosed display substrate can comprise: a thin film transistor substrate; a plurality of micro LEDs arranged on one surface of the thin film transistor substrate; a rear substrate having one surface coupled to the other surface of the thin film transistor substrate, and having at least a part of an edge protruding further than the edge of the thin film transistor substrate so as to form a stepped part together with the thin film transistor substrate; and a plurality of wirings formed on the stepped part and the other surface of the rear substrate so as to electrically connect the one surface of the thin film transistor substrate and the other surface of the rear substrate.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.

Abstract: Some embodiments relate to a semiconductor device disposed on a semiconductor substrate. A dielectric structure is arranged over the semiconductor substrate. First and second metal vias are disposed in the dielectric structure and spaced laterally apart from one another. First and second metal lines are disposed in the dielectric structure and have nearest neighboring sidewalls that are spaced laterally apart from one another by a portion of the dielectric structure. The first and second metal lines contact upper portions of the first and second metal vias, respectively. First and second air gaps are disposed in the portion of the dielectric structure. The first and second air gaps are proximate to nearest neighboring sidewalls of the first and second metal lines, respectively.

Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: Present disclosure provides a FinFET structure, including a substrate, a fin protruding from the substrate, including a first portion and a second portion below the first portion, wherein the first portion includes a first dopant concentration of a dopant, and the second portion includes a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration, a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate, and an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer includes a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A display substrate and a display apparatus are provided, the display substrate includes a base substrate including a display region and a peripheral region; the display region includes multiple sub-pixels, multiple data lines and multiple power supply lines; the peripheral region includes at least one test data signal line, at least one test control signal line and multiple test units, the multiple test units are at a side of the multiple data lines away from the display region, and at least one of the multiple test units is electrically connected with at least one of the multiple data lines, the at least one test data signal line, and the at least one test control signal line; the peripheral region further includes a first power supply bus and multiple connecting parts, the first power supply bus is at a side of the multiple test units away from the display region.

Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

Abstract: A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.