Patents Examined by Theresa T. Doan
  • Patent number: 10559734
    Abstract: Disclosed are a light emitting device package. The light emitting device package includes a body having recess; a first lead frame including a first and second portions on a first region of the body; a second lead frame including a third and fourth portions on a second region of the body; a third lead frame between the first and second lead frame. The body has a length of the first direction greater than a width of the second direction, wherein the second portion of the first lead frame extends toward the second lead frame and has a small width, and wherein the fourth portion of the second lead frame extends toward the first lead frame. A first light emitting device is disposed on the first portion of the first lead frame and a second light emitting device is disposed on the third portion of the second lead frame.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: February 11, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventor: Dong Yong Lee
  • Patent number: 10553591
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho
  • Patent number: 10549982
    Abstract: A packaged pressure sensor, comprising: a MEMS pressure-sensor chip; and an encapsulating layer of elastomeric material, in particular PDMS, which extends over the MEMS pressure-sensor chip and forms a means for transferring a force, applied on a surface thereof, towards the MEMS pressure-sensor chip.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: February 4, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Enri Duqi, Bruno Murari, Sebastiano Conti
  • Patent number: 10546807
    Abstract: Disclosed are a chip on film (COF) and a display device including the same, for reducing the number of input pads using a pattern branching structure. The COF is connected to gate-in-panel (GIP) output pads using a structure formed via branching of GIP wirings connected to the GIP input pads in a data driving integrated circuit (IC) or a circuit film to reduce the number of GIP input pads.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: January 28, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Soon-Dong Cho, Hoon Jang, Min-Gyu Park, Won-Yong Jang
  • Patent number: 10541237
    Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee
  • Patent number: 10535595
    Abstract: Embodiments are generally directed to a conductive base embedded interconnect. An embodiment of an apparatus includes a substrate; an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts; and one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Adel A. Elsherbini
  • Patent number: 10532922
    Abstract: A micro-electro-mechanical actuator device includes a fixed structure and a mobile structure. The mobile structure includes a first deformable band, a second deformable band, and a third deformable band, both of which extend on opposite sides of the first deformable band, each of which carries a piezoelectric actuator. In a working condition, in which the second and third piezoelectrics are biased, the second and third deformable bands are subjected to a negative bending, while the first deformable band is subjected to a positive bending. There are thus generated two translations that add together, causing a displacement of the first deformable band greater than the one that may be obtained by a single membrane of an equal base area.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Domenico Giusti, Carlo Luigi Prelini
  • Patent number: 10522622
    Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
  • Patent number: 10522345
    Abstract: A method includes receiving a semiconductor substrate including a first semiconductor material; etching a portion of the semiconductor substrate, thereby forming a recess, a bottom portion of the recess having a first sidewall and a second sidewall intersecting with each other, one of the first and second sidewalls exposing a (111) crystallographic plane of the semiconductor substrate; and epitaxially growing a second semiconductor material in the recess, the second semiconductor material having lattice mismatch to the first semiconductor material, dislocations in the second semiconductor material due to the lattice mismatch propagating from the first sidewall to the second sidewall in a direction parallel to a top surface of the semiconductor substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hsien Wu, I-Sheng Chen
  • Patent number: 10504987
    Abstract: A flexible display device includes: a flexible substrate; a photo-curable adhesive layer disposed on the flexible substrate; and a metal wiring disposed on the photo-curable adhesive layer. The metal wiring defines a plurality of holes. The flexible display device and a method of manufacturing the flexible display device may substantially prevent detachment of the metal wiring formed on the flexible substrate.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 10, 2019
    Assignees: SAMSUNG DISPLAY CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sangyoun Han, Kyungseop Kim, Jungyong Lee, Kiwon Seo
  • Patent number: 10504810
    Abstract: A structure includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die, and a cavity in the encapsulating material. The cavity penetrates through the encapsulating material.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai
  • Patent number: 10497712
    Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
  • Patent number: 10497792
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 10490667
    Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu, Nicolas J. Loubet
  • Patent number: 10483124
    Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masakazu Sawano, Takahiro Tomimatsu, Junichi Shibata, Hideki Inokuma, Hisashi Kato, Kenta Yoshinaga
  • Patent number: 10475811
    Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10475929
    Abstract: A method of manufacturing a semiconductor device includes forming a nanowire foundation layer on a semiconductor substrate. A first nanowire is formed on the nanowire foundation layer. A gate structure is formed over the nanowire foundation layer and wrapping the first nanowire. A second nanowire is formed on and in contact with the first nanowire in a bottom-up manner. A source/drain region is formed on the gate structure and wrapping the second nanowire.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Mark Van Dal
  • Patent number: 10468384
    Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 5, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, SungSoo Kim, HeeSoo Lee
  • Patent number: 10468503
    Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Jeng-Bang Yau, Alexander Reznicek, Tak H. Ning
  • Patent number: 10468308
    Abstract: An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Jr-Jung Lin, Chun-Hung Lee