Abstract: A display substrate and a display apparatus are provided, the display substrate includes a base substrate including a display region and a peripheral region; the display region includes multiple sub-pixels, multiple data lines and multiple power supply lines; the peripheral region includes at least one test data signal line, at least one test control signal line and multiple test units, the multiple test units are at a side of the multiple data lines away from the display region, and at least one of the multiple test units is electrically connected with at least one of the multiple data lines, the at least one test data signal line, and the at least one test control signal line; the peripheral region further includes a first power supply bus and multiple connecting parts, the first power supply bus is at a side of the multiple test units away from the display region.
Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.
Abstract: A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.
Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.
July 23, 2021
Date of Patent:
February 13, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.
Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
November 7, 2022
Date of Patent:
February 6, 2024
Micron Technology, Inc.
Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.
Abstract: The present application discloses a capacitor integrated in a FinFET. The capacitor and a resistor are both integrated in a middle-end-of-line process layer. A resistor main body layer and a resistor cover layer of the resistor and the forming regions of the intermediate dielectric layer and the lower electrode plate of the capacitor are patterned in a lithography process applying a first photomask; a forming region of an upper electrode plate is patterned in another lithography process applying a second photomask; the lower electrode plate, the upper electrode plate and the resistor main body layer are respectively connected with a metal zeroth layer. The present application further discloses a method for fabricating a capacitor integrated in a FinFET device. The disclosed method can reduce the process cost and improve the process efficiency, as well as flexibly select the capacitance of the capacitor by the process.
Abstract: The present invention provides a semiconductor manufacturing method. A substrate having a plurality of first trenches can be provided. The substrate can include a first pattern formed between two adjacent first trenches. A first dielectric layer can be deposited onto the substrate. The first dielectric layer can cover at least one side wall of the first pattern. A second dielectric layer can be deposited onto the substrate. The second dielectric layer can fill the first trenches. The first pattern can be severed to form a second pattern on the substrate. The second dielectric layer can be removed from the first trenches.
Abstract: A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.
Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.
Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.
Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.
September 8, 2021
Date of Patent:
December 26, 2023
Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.
Abstract: A semiconductor structure includes a substrate and a field effect transistor disposed on the substrate. The field effect transistor includes a vertical fin, source and drain regions separated by a gate region, a gate structure disposed over the gate region and a gate airgap spacer at least partially disposed about the gate structure.
September 27, 2021
Date of Patent:
December 19, 2023
International Business Machines Corporation
Ruilong Xie, Julien Frougier, Kangguo Cheng, Chanro Park
Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.
Abstract: Embodiments of the present disclosure provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a base including an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, a top opening area of the first isolation structure being greater than that of the second isolation structure; the first isolation structure having a first groove, and a first insulation structure configured to fill the first groove; and the first insulation structure including at least a top isolation layer, a top surface of the top isolation layer being flush with a top surface of the base, and the top isolation layer being made of at least a low dielectric constant material.