Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

Abstract: The present disclosure relates to a solid-state image pickup element in order to enable inhibition of a variation in the photoelectric conversion characteristic of an organic photoelectric conversion film due to atmospheric exposure and a manufacturing method of the solid-state image pickup element, and an electronic device. The solid-state image pickup element includes: a photoelectric conversion film formed above a semiconductor substrate; and a sidewall sealing a side face of the photoelectric conversion film. The sidewall includes a re-deposited film of a film directly under the sidewall. The present disclosure is applicable to, for example, a CMOS image sensor or the like.

Abstract: A through electrode substrate includes: a substrate including first and second surfaces respectively on a first side and a second side opposite to the first, the substrate having a through hole; and a through electrode. The through electrode has a sidewall portion along the through hole sidewall, and a first portion the first surface and connected to the sidewall portion. The through electrode substrate includes: an organic film inside the through hole; an inorganic film that at least partially covers the through electrode first portion from the first side and has an opening on the first portion; and a first wiring layer having an insulation layer to the inorganic film first side and includes an organic layer with an opening communicating with the inorganic film opening, and an electroconductive layer connected to the through electrode first portion through the inorganic film opening and the insulation layer opening.

Abstract: A semiconductor device that includes a semiconductor substrate having a surface, the surface having several regions having different thermal and/or mechanical requirements; and a composite thermal interface material including several spatially localized thermal interface materials placed on the surface, each of the several thermal interface materials tailored to the different thermal and/or mechanical requirements of each of the regions. Also disclosed is a method of forming the composite thermal interface material.

Abstract: A membrane component comprises a membrane structure comprising an electrically conductive membrane layer. The electrically conductive membrane layer has a suspension region and a membrane region. In addition, the suspension region of the electrically conductive membrane layer is arranged on an insulation layer. Furthermore, the insulation layer is arranged on a carrier substrate. Moreover, the membrane component comprises a counterelectrode structure. A cavity is arranged vertically between the counterelectrode structure and the membrane region of the electrically conductive membrane layer. In addition, an edge of the electrically conductive membrane layer projects laterally beyond an edge of the insulation layer by more than half of a vertical distance between the electrically conductive membrane layer and the counterelectrode structure.

Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.

Abstract: A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes: providing a semiconductor structure comprising: an interlayer dielectric layer, a first metal layer surrounded by the interlayer dielectric layer, and a semiconductor layer on the interlayer dielectric layer; etching the semiconductor layer to form an opening exposing the interlayer dielectric layer, wherein the opening comprises a first opening and a second opening on the first opening; forming an insulation layer on the semiconductor structure; etching the insulation layer and the interlayer dielectric layer at the bottom of the first opening to form a groove exposing a portion of the first metal layer; forming a second metal layer on the insulation layer and on the bottom and a side surface of the groove; and patterning the second metal layer. The second metal layer in this inventive concept can be removed more completely than conventional methods.

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: A semiconductor chip, a method for producing a semiconductor chip and an apparatus having a plurality of semiconductor chips are disclosed. In an embodiment a chip includes a substrate and a semiconductor layer arranged at the substrate, wherein the substrate includes, at a side facing the semiconductor layer, a top side with a width B1 in a first lateral direction and, at a side opposite to the top side, a bottom side with a width B3 in the first lateral direction, wherein the substrate has a width B2 in the first lateral direction at a half height between the top side and the bottom side, and wherein the following applies to widths B1, B2 and B3: B1?B2<B2?B3, and B1?B2>B3.

Abstract: A buried word line structure including a substrate, an isolation structure, and a buried word line is provided. The isolation structure is located in the substrate to define active regions separated from each other. The active regions extend in a first direction. The buried word line is located in the substrate. The buried word line extends through the isolation structure and the active regions in a second direction. The first direction intersects the second direction. The buried word line and the substrate are isolated from each other. The same buried word line includes a first portion and a second portion. The first portion is located in the active regions. The second portion is located in the isolation structure between two adjacent active regions in the first direction. A width of the first portion is greater than a width of the second portion.

Abstract: The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.

Abstract: An IC with a split-gate transistor includes a substrate doped the second conductivity type having a semiconductor surface layer doped the first conductivity type. The transistor includes a first doped region formed as an annulus, a second doped region including under the first doped region, and a third doped region under the second doped region, all coupled together and doped the second conductivity type. A fourth doped region doped the first conductivity type is above the third doped region. A fifth doped region doped the first conductivity type is outside the annulus. Sixth doped regions doped the first conductivity type include a first sixth doped region surrounded by the annulus in the semiconductor surface layer and a second sixth doped region in the fifth doped region. Field oxide includes a field oxide portion between the fifth and the first doped region. A field plate is on the field oxide portion.

Abstract: A method for bonding a semiconductor package includes loading a semiconductor chip on a substrate, and bonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface. Bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, and deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface.

Abstract: A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.

Abstract: The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

Abstract: A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.