Patents Examined by Thien D Nguyen
  • Patent number: 9934871
    Abstract: Described here in are systems, methods and, software to verify storage media and storage subsystems upon deployment. In one example, a computer apparatus to test storage media in a storage subsystem includes processing instructions that direct a computing system to identify initiation of a storage subsystem, initiate a testing process of the storage media, and identify a partition availability event for the storage media. The processing instructions also direct the computing system to, in response to the partition availability event, make a partition of the storage media available to a host processing system, wherein the partition comprises storage locations in the storage media tested via the testing process, and continue the testing process on the storage media. The computer apparatus also includes one or more non-transitory computer readable media that store the processing instructions.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: April 3, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Christopher Squires
  • Patent number: 9921899
    Abstract: A serial link data monitoring apparatus for targeting a given Bit Error Rate (BER) for stable serial link data communication is disclosed. An interface unit may be configured to receive data via a serial interface, and circuitry may be configured to monitor errors in the data. The circuitry may be further configured to perform one or more first training operations in response to a determination that the number of errors detected in the data is greater than a first threshold value, and perform a second training operation in response to a determination that a number of first training operations performed in a predetermined period of time is greater than a second threshold value. An amount of time to perform the second training operation may be greater than an amount of time to perform a given one of the first training operations.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 20, 2018
    Assignee: Oracle International Corporation
    Inventors: Michelle Wong, Dawei Huang, Thomas Wicki, Albert Martin
  • Patent number: 9910728
    Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: March 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Debaleena Das, Rajat Agarwal, Brian S. Morris
  • Patent number: 9910086
    Abstract: A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 6, 2018
    Inventors: Allen Czamara, Ed Paulsen, Lev Alperovich
  • Patent number: 9897653
    Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Bruno Fel
  • Patent number: 9865362
    Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 9, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Puneet Arora, Steven Lee Gregor, Norman Robert Card, Navneet Kaushik
  • Patent number: 9857424
    Abstract: An automated test equipment includes a test processor configured to provide a signal to a device under test on the basis of a sequence of instructions defining an evaluation of test vectors. The test processor is configured to map a test vector onto a set of signal states or signal transitions. Furthermore, the test processor is configured to variably select a number of signal states or signal transitions provided in the signal based on a current test vector in dependence on a current instruction.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 2, 2018
    Assignee: Advantest Corporation
    Inventor: Kazi Iftekhar Ahmed
  • Patent number: 9852808
    Abstract: A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 26, 2017
    Assignee: Shanghai Huanhong Grace Semiconductor Manufacturing Corporation
    Inventor: Liang Qian
  • Patent number: 9835685
    Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 5, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Gen Oshiyama, Takahiro Shikibu, Osamu Moriyama, Iwao Yamazaki, Akihiro Chiyonobu
  • Patent number: 9835683
    Abstract: An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of X-bounding circuitry inserted into the IC can be drastically reduced compared to that required by conventional X-bounding methodologies.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, INC.
    Inventors: Priya Khandelwal, Himanshu Arora, Abhilash Kaushal
  • Patent number: 9837027
    Abstract: The semiconductor device cyclically outputs given status information pieces according to a predetermined procedure from a test output terminal one by one on receipt of a test enable direction through a test enable terminal, and outputs the same status information pieces as those output at that time from the test output terminal without interruption on receipt of a test disable direction. Operating the test enable terminal, the semiconductor device cyclically outputs status information pieces without the need for initial setting and further, outputs only desired status information without interruption.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 5, 2017
    Assignee: Synaptics Japan GK
    Inventors: Akihito Kumamoto, Kazuo Nishimae
  • Patent number: 9838159
    Abstract: A method, a device, and a non-transitory storage medium having instructions to receive data and first channel information pertaining to a transmission of the data; store first constellation data and demodulate the data; determine whether any error exists pertaining to the data; receive retransmitted data and second channel information when an error exists; demodulate the retransmitted data; calculate error vector magnitude data; generate corrective constellation data based on the error vector magnitude data, the first channel information, and the second channel information, wherein the corrective constellation data includes at least one reference constellation point that is repositioned on a constellation plane relative to at least one corresponding reference constellation point of a default constellation data; and use the corrective constellation data when demodulating additional data that is subsequently received.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 5, 2017
    Assignee: Verizon Patent and Licensing Inc.
    Inventor: Donna L. Polehn
  • Patent number: 9829536
    Abstract: In one embodiment, a multiple input signature register (MISR) shadow works with a MISR to compress test responses of a layout partition in a functional region of an integrated circuit. In operation, for each test pattern in a test pattern split, the MISR generates a MISR signature based on the responses of the layout partition. As the test patterns in the test pattern split execute, the MISR shadow accumulates the MISR signatures and stores the result as MISR shadow data. After the final test pattern included in the test pattern split executes, the MISR shadow combines the bits in the MISR shadow data to form a single bit MISR shadow status that indicates whether the layout partition, and therefore the functional region, responds properly to the test pattern split. By efficiently summarizing the test responses, the MISR shadow optimizes the resources required to identify defective functional regions.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 28, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Jonathon E. Colburn, Amit Sanghani
  • Patent number: 9831002
    Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 28, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Patent number: 9804225
    Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 31, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Saurabh Kumar Singh, Balwant Singh
  • Patent number: 9797948
    Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Milan Shetty, Srinivasulu Alampally, Prasanth V
  • Patent number: 9797949
    Abstract: A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 24, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Gen Oshiyama, Osamu Moriyama, Takahiro Shikibu, Akihiro Chiyonobu, Iwao Yamazaki
  • Patent number: 9786356
    Abstract: A method of operation of a memory device includes, for each operating frequency of multiple operating frequencies, determining a target voltage level of a supply voltage. For example, a first target voltage level for a first operating frequency of the multiple operating frequencies is determined. The method includes accessing first data from the memory device while the memory device is operating at the first operating frequency and is powered by the supply voltage having a first voltage level. The method includes determining a first number of errors associated with the first data. The method further includes, in response to the first number of errors satisfying a threshold, adjusting the supply voltage to a second voltage level that is greater than the first voltage level.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Niladri Narayan Mojumder, Jonathan Liu, Choh Fei Yeap
  • Patent number: 9779838
    Abstract: A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 3, 2017
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Joon-Sung Yang, Hyunseung Han
  • Patent number: 9754683
    Abstract: An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Matthew Goldman, Krishna K. Parat, Pranav Kalavade, Nathan R. Franklin, Mark Helm