Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.

Abstract: An apparatus, system, and method are disclosed for providing error correction for a data storage device. A determination module determines an error-correcting code (“ECC”) characteristic of the data storage device. An ECC module validates requested data read from the data storage device using a hardware ECC decoder. In response to the requested data satisfying a correction threshold, a software ECC decoder module validates the data using a software ECC decoder. The software ECC decoder is configured according to the ECC characteristic of the data storage device.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

Abstract: Apparatus having corresponding methods and computer-readable media comprise a function module to operate according to a clock signal; a clock control module to provide a clock gate signal; and a clock gate module to provide the clock signal to the function module only until the clock control module provides the clock gate signal; wherein the function module includes a plurality of storage elements, wherein the storage elements form a scan chain in response to a mode signal; and wherein the scan chain is configured to shift data stored therein out of the scan chain.

Abstract: Consistent the present disclosure, errored bits are inserted into a data stream, which is carried by an optical signal. The optical signal is transmitted over an optical link that may induce additional errors, i.e., add additional errored bits to the data stream. At the receive end, the optical signal is converted into a corresponding electrical signal that carries the data stream. The data stream is subject to forward error correction (FEC) decoding with an iterative decoder, for example. The iterative decoder decodes the data stream over a number of iterations until both the inserted errored bits and the additional errored bits are corrected. Since the number of inserted bits is known, the number of iterations required to correct the inserted bits is also known (“first iterations”).

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing.

Abstract: A method of encoding that uses standard codecs such as linear encoders and decoders for encoding and decoding data with different levels of robustness to errors is described. In one configuration, multiple encoders may be utilized, and one of the encoders may use a standard encoder such as a turbo code followed by a nonlinearity that creates an unequal distribution of ones and zeros in a binary representation of the code. In another configuration, a coder may be utilized that represents message outputs as “channels” that create state transitions (or symbol errors) in a data forward error correction coder.

Abstract: Disclosed are a wireless transmission device, wireless receiving device, and method for transmitting encoded data with which power consumption can be reduced at the receiving end in accordance with reception conditions, while resource-saving is maintained by employing an erasure correcting code (ECC).

Abstract: An improved data storage technique achieves a desired level of reliability by providing sufficient redundancy in erasure coded data to maintain the data, without repair, for a prescribed period of time. The improved technique employs a newly devised, continuous-time Markov chain model. The model can be applied in computerized systems to establish erasure coding parameters for storing and reliably maintaining data for a designated period of time, without any need to repair the data to reestablish an original or previous level of erasure coding redundancy.

Abstract: The present disclosure discloses a method and a device for bandwidth self-adapting data ranking protection. The method comprises: performing redundancy protection computation on a data block to be transmitted so as to generate a redundant code of the data block, and setting a priority for the redundant code; determining whether bandwidth occupied by a redundant code with a highest priority is greater than current residual bandwidth; if the bandwidth occupied by the redundant code with the highest priority is not greater than the current residual bandwidth, carrying the redundant code with the highest priority in the current residual bandwidth; otherwise, according to a descending order of the priority, searching in residual redundant codes for a redundant code whose data amount is less than or equal to the current residual bandwidth, and carrying a found redundant code in the current residual bandwidth. The present disclosure improves the error tolerance of a system.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m?1 is received. A code word with length N=2m?1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: A method implemented in a digital subscriber line (DSL) system is described for minimizing a misdetection probability at a far-end coded message receiver during transmission of a coded message. The method comprises jointly determining, at the far-end coded message receiver, a P matrix and a modulation scheme. The method further comprises encoding a message into a coded message with a systematic linear block code, the systematic linear block code having a generator matrix [I P], where I represents a linear block code component identity matrix and P represents the determined P matrix. The method also comprises modulating the encoded message to one or more tones forming a discrete multi-tone (DMT) symbol according to the determined modulation scheme.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.