Abstract: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.

Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.

Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.

Abstract: Disclosed is a manufacturing method of a photo spacer structure of an array substrate, including: forming first pad carriers and second pad carriers having height difference; depositing black photosensitive resin material to cover the first pad carriers and the second pad carriers; implementing exposure to the black photosensitive resin material through a mask, having light transmitting areas and light shielding areas, and light transmission adjusting parts are arranged corresponding to the second pad carriers, and implementing development to form main photo spacers on the first pad carriers, sub photo spacers on the second pad carriers and grooves or trenches in areas around the sub photo spacer with the light transmission adjusting parts; implementing a high-temperature baking and leveling treatment to the black photosensitive resin material to level and fill at least a portion of the resin material of the sub photo spacers to the grooves or the trenches.

Abstract: A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate.

Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a first surface, a second surface, and a light-sensing region. The image sensor device includes a first isolation structure in the substrate and adjacent to the first surface. The first isolation structure surrounds the light-sensing region. The image sensor device includes a second isolation structure passing through the first isolation structure and the substrate under the first isolation structure. The second isolation structure surrounds the light-sensing region and a portion of the first isolation structure.

Abstract: A wafer processing method includes a protective film providing step of providing a protective film on the front side of a wafer, a wafer unit forming step of applying a liquid resin curable by an external stimulus to the front side of the wafer and then curing the liquid resin by applying the external stimulus to form a protective member, thereby forming a wafer unit composed of the wafer, the protective film, and the protective member in the condition where the front side of the wafer is covered with the protective member, a grinding step of holding the protective member on a holding surface of a chuck table and then grinding the back side of the wafer of the wafer unit to thereby reduce the thickness of the wafer, and a peeling step of peeling the protective member and the protective film from the wafer reduced in thickness.

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.

Abstract: A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

Abstract: Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.

Abstract: Disclosed is a method for improving transmittance of flat or curved liquid crystal display panel. The method includes the following steps. (1) A substrate is manufactured according to the BPS technology. The substrate includes an array substrate and a CF substrate. A spacer and a black matrix are provided on a side of the array substrate and a transparent conductive electrode film is provided on a side of the CF substrate. (2) Marks are engraved on designated positions of the CF substrate by means of a laser and the CF substrate is aligned with the marks on a platform of a UV2A exposure machine. (3) Tracking lines are engraved on the transparent conductive electrode film and a region bounded by the tracking lines is aligned with a light-shielding region of a gate line or a light-shielding region of a data line on the side of the array substrate. (4) The substrate is exposed to light and a mask is used to track the tracking lines.

Abstract: A method of processing a wafer includes applying a laser beam having a wavelength that is transmittable through a sapphire substrate to the wafer while positioning a focused spot of the beam within the wafer in regions corresponding to projected dicing lines through a reverse side of the wafer, thereby forming a plurality of shield tunnels made up of a plurality of pores and an amorphous body surrounding the pores, at predetermined spaced intervals in the wafer along the projected dicing lines. A laser beam having a wavelength that is transmittable through the sapphire substrate to the wafer is applied while positioning a focused spot of the laser beam within the wafer in the projected dicing lines through the reverse side of the wafer, thereby forming modified layers between adjacent shield tunnels. Exerting external forces to the wafer divides the wafer into a plurality of optical device chips.

Abstract: An OLED display device includes a substrate including red, green, and blue pixel areas, a first electrode at each of the red pixel area, the green pixel area, and the blue pixel area on the substrate, a hole transport layer on the first electrode, a light emission portion on the hole transport layer, the light emission portion including a red light emitting layer at the red pixel area, a green light emitting layer at the green pixel area, and a blue light emitting layer at the blue pixel area, a first charge generation layer and a first resonance auxiliary layer between the hole transport layer and the blue light emitting layer, a second resonance auxiliary layer between the hole transport layer and the red light emitting layer, an electron transport layer on the light emission portion, and a second electrode on the electron transport layer.

Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

Abstract: A manufacturing method of a package structure having an embedded bonding film comprises the following steps: forming a bonding film, forming a redistribution substrate and forming a core on a bottom side of the redistribution substrate opposite to the top side. The bonding film comprises the following steps: forming a plurality of dielectric layers and metal circuit layers sequentially and alternatively in a plurality of bonding areas; exposing a plurality of top metal pads of a topmost metal circuit layer among the metal circuit layers in the plurality of bonding areas; and etching to form a bonding film. The bonding film has a left longitudinal branch and a lower latitudinal branch. A lower end of the left longitudinal branch is connected to a left end of the lower latitudinal branch. The left longitudinal branch and the lower latitudinal branch form an L shape.

Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

Abstract: The present application discloses a method of fabricating a quantum dots light emitting diode, the method including co-depositing an electron transport material and an inorganic perovskite material on a base substrate to form a composite layer having the electron transport material and the inorganic perovskite material.