Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.

Abstract: Described herein is a method and system for dual stretching of wafers to create isolated segmented chip scale packages. A wafer having an array of light-emitting diodes (LEDs) is scribed into LED segments, where each LED segment includes a predetermined number of LEDs. The scribed wafer is placed on a stretchable substrate or tape. The tape is stretched and a layer of optically material is placed in the separation gaps. The stretched wafer is scribed on a LED level. The tape is stretched and another layer of optically opaque material is placed in the separation gaps. The same or different optically opaque material can be used for the layers. The two layers of optically opaque material are formed to provide electrical connectivity between the LEDs in each LED segment. In an implementation, each segment or LED is individually addressable.

Abstract: The invention relates to a cassette holder assembly for holding a cassette for storing at least one semiconductor material substrate in an interior space accessible from a front end of the cassette. The cassette holder assembly may have a base plate for receiving the cassette. Two holding members supported by the base plate may be positioning the cassette on the plate in the assembly. The holding members may be substantially identical to each other.

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing thereof capable of relaxing a level difference thereon. A semiconductor device according to the present invention includes a first interlayer insulating film having a first opening, and a second interlayer insulating film having a second opening wherein a following expression is satisfied: (H2?H1)/((W2?W1)/2)?3.6 where, in sectional view, W1 represents a width of the first opening, W2 represents a width of the second opening, H1 represents a minimum value of a height from a surface of the semiconductor substrate to a surface of the third interlayer insulating film in the second opening, and H2 represents a height from the surface of the semiconductor substrate to the surface of the third interlayer insulating film in an end of the second opening.

Abstract: Methods and systems for tracking an edge ring includes capturing an edge ring identifier from a source related to the edge ring. The edge ring is inserted into a slot of an edge ring carrier, wherein the edge ring is being assigned to the edge ring carrier. The edge ring identifier is tracked to determine transfers into and out of the edge ring carrier and into and out of a processing station. The tracking of the edge ring identifier builds a metadata file that provides lifetime information regarding the edge ring.

Abstract: A laser annealing device includes: a CW laser device configured to emit continuous wave laser light caused by continuous oscillation to preheat the amorphous silicon; a pulse laser device configured to emit the pulse laser light toward the preheated amorphous silicon; an optical system configured to guide the continuous wave laser light and the pulse laser light to the amorphous silicon; and a control unit configured to control an irradiation energy density of the continuous wave laser light so as to preheat the amorphous silicon to have a predetermined target temperature less than a melting point thereof, and configured to control at least one of a fluence and a number of pulses of the pulse laser light so as to crystallize the preheated amorphous silicon.

Abstract: A method for depositing a silicon nitride film is provided to fill a recessed pattern formed in a surface of a substrate. In the method, a first adsorption blocking region is formed by adsorbing first chlorine radicals such that an amount of adsorption increases upward from a bottom portion of the recessed pattern. A source gas that contains silicon and chlorine adsorbs on an adsorption site where the first adsorption site is not formed. A molecular layer of a silicon nitride film is deposited so as to have a V-shaped cross section. A second adsorption blocking region is formed by adsorbing second chlorine radicals on the molecular layer of the silicon nitride film. The molecular layer of the silicon nitride film is modified by nitriding the molecular layer while removing the second adsorption blocking region.

Abstract: A semiconductor device includes a plurality of broad buffer layers provided in a drift layer. Each of the plurality of the broad buffer layers has an impurity concentration exceeding that of a portion of the drift layer excluding the broad buffer layers, and has a mountain-shaped impurity concentration distribution in which a local maximum value is less than the impurity concentration of an anode layer and a cathode layer. The plurality of broad buffer layers are disposed at different depths from a first main surface of the drift layer, respectively, the number of broad buffer layers close to the first main surface from the intermediate position of the drift layer is at least one, and number of broad buffer layers close to a second main surface of the drift layer from the intermediate position of the drift layer is at least two. The broad buffer layer includes a hydrogen-related donor.

Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.

Abstract: Methods comprising depositing a film material to form an initial film in a trench in a substrate surface are described. The film is treated to expand the film to grow beyond the substrate surface.

Abstract: The present invention relates to a micro LED grip body for vacuum-sucking micro LEDs. More particularly, the present invention relates to a micro LED grip body provided with a mask below a porous member to increase vacuum pressure for vacuum-sucking micro LEDs such that the micro LEDs are transferred without deviation.

Abstract: Disclosed herein are optical stacks that are stable to light exposure by incorporating one or more UV-blocking layers.

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

Abstract: A storage device includes a conductive layer, a plurality of electrode layers stacked on the conductive layer, a wiring above the plurality of electrode layers, an interlayer insulating film between the plurality of electrode layers and the wiring, a semiconductor film penetrating the plurality of electrode layers and the interlayer insulating film in a stacking direction of the plurality of electrode layers, a contact plug penetrating the interlayer insulating film in the stacking direction, and connected to each of the plurality of electrode layers, and a conductive film in the vicinity of the contact plug and penetrating at least one of the plurality of electrode layers in the stacking direction. The semiconductor film is electrically connected to the conductive layer and the wiring, and an entire upper end of the conductive film is covered by an insulating layer.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Abstract: In an active region, a gate electrode is disposed in a trench. Spaced apart from the gate electrode, an emitter electrode is disposed in the trench. A source diffusion layer and a base diffusion layer are formed in the active region. The base diffusion layer has a base bottom portion inclined in such a manner that a portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a portion of the base bottom portion adjacent to the gate electrode. A contact portion has a contact bottom portion inclined in such a manner that a portion of the contact bottom portion in contact with the emitter electrode is positionally deeper than a portion of the contact bottom portion in contact with the base diffusion layer.