Abstract: In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

Abstract: Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.

Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

Abstract: A method for fabricating a liquid crystal display device includes: forming a pixel electrode on a substrate; forming a first conductive layer on the pixel electrode; forming a first photoresist pattern on the conductive layer; forming a source electrode forming portion, a channel forming portion and a pixel electrode forming portion using the first photoresist pattern as a mask; forming a semiconductor layer over an entire surface of the substrate; forming an insulating layer on the semiconductor layer; forming a second conductive layer on the insulating layer; forming a second photoresist pattern on the second conductive layer; forming an active layer using the second photoresist pattern; and forming a gate electrode on the active layer.

Abstract: A micromechanical device comprising one or more electronically movable structure sets comprising for each set a first electrode supported on a substrate and a second electrode supported substantially parallel from said first electrode. Said second electrode is movable with respect to said first electrode whereby an electric potential applied between said first and second electrodes causing said second electrode to move relative to said first electrode a distance X, (X), where X is a nonlinear function of said potential, (V). Means are provided for linearizing the relationship between V and X.

Abstract: A flat panel display is provided. The flat panel display includes a light emitting device and two or more thin film transistors (TFTs) having semiconductor active layers having channel regions, where the thickness of the channel regions of the TFTs are different from each other. Thus, higher switching properties of a switching TFT can be maintained, a more uniform brightness of a driving TFT can be satisfied, and a white balance can be satisfied without changing a size of the TFT active layer.

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

Abstract: A method to electronically modulate the energy gap and band-structure of semiconducting carbon nanotubes is proposed. Results show that the energy gap of a semiconducting nanotube can be narrowed when the nanotube is placed in an electric field perpendicular to the tube axis. Such effect in turn causes changes in electrical conductivity and radiation absorption characteristics that can be used in applications such as switches, transistors, photodetectors and polaron generation. By applying electric fields across the nanotube at a number of locations, a corresponding number of quantum wells are formed adjacent to one another. Such configuration is useful for Bragg reflectors, lasers and quantum computing.

Abstract: A semiconductor sensing device in which a sensing layer is exposed to a medium being tested in an area below and/or adjacent to a contact. In one embodiment, the device comprises a field effect transistor in which the sensing layer is disposed below a gate contact. The sensing layer is exposed to the medium by one or more perforations that are included in the gate contact and/or one or more layers disposed above the sensing layer. The sensing layer can comprise a dielectric layer, a semiconductor layer, or the like.

Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

Abstract: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The stacked multiple offset chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Abstract: Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.

Abstract: The invention provides a semiconductor integrated circuit which allows a plurality of devices to be integrated compactly, that is, with high density; a signal transmitting device; an electro-optical device; and an electronic apparatus. A semiconductor integrated circuit includes tile-shaped microelements that are superimposed upon and adhered to the top surface of a substrate with an adhesive.

Abstract: A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulating layer is removed to form a one-dimensional slot and to provide access to the active regions. A bit line is then formed in the slot in contact with the active regions.

Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.

Abstract: A method of producing nitride based heterostructure devices by using a quaternary layer comprised of AlInGaN. The quaternary layer may be used in conjunction with a ternary layer in varying thicknesses and compositions that independently adjust polarization charges and band offsets for device structure optimization by using strain compensation profiles. The profiles can be adjusted by altering profiles of molar fractions of In and Al.