Programmable random logic arrays using PN isolation
Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.
Latest IBM Patents:
1. Field of the Invention
This invention generally relates to integrated circuits. More specifically, the invention relates to random logic integrated circuit devices, and to methods for making such circuits.
2. Background Art
Integrated circuits are an essential part of digital systems, such as computers. One challenge to the manufacturers of such circuits is to provide each customer with a circuit that is or can be tailored to the specific needs of that customer.
There are several ways to address this challenge. One way is to provide circuits that are programmable or have random logic. Logic can be designed and fixed, as in a gate array (GA) device, so that earlier, or “front end” (FE), process steps used in the manufacture of the circuits are quite generic, in particular, with respect to implantation and contact. Personalization of the devices can be entirely or substantially accomplished in the later, or “back end” (BE), metalization steps used in the manufacture of the circuit.
Further, logic can be re-programmed, as in field programmable gate arrays (FPGAs). Alternatively, the logic can be defined real-time, yielding a dynamically reconfigurable/random logic device.
While various ways are known to provide random logic, they tend to require relatively complex designs and manufacturing processes.
SUMMARY OF THE INVENTIONAn object of this invention is to improve programmable random logic array devices and methods for making such devices.
Another object of the present invention is to use PN isolation in a programmable random logic array.
A further object of the invention is to provide an ordered array of spaced apart PN junctions to form a programmable device array.
These and other objectives are attained with a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer.
The programmable, random, logic device array further comprises first and second sets of contacts. Each of the first set of contacts is above and in electrical contact with a respective one area of said first region of the semiconductor layer, and each of the second set of contacts is above and in electrical contact with a respective one of the second regions. In this way, the electrical contacts facilitate connecting together said areas of the first region and the second regions in various, programmable ways.
The preferred embodiment of the invention has a number of important advantages, and can be provided with a number of additional features. For example, in one method for making the logic array, front-end processes (e.g., implantation, active devices) are generic or substantially generic, some are common between multiple devices, and devices can be defined into specific types by hard-wire (netlist). Also, the active devices of the logic array may be PN junctions formed adjacent to one another so that their overlap regions form a space-charge region, thus isolating one device from another (in two or three dimensions).
In addition, in the preferred procedure for making the logic array, the front-end devices can be formed over an entire wafer or regions of fixed or arbitrary geometry. Personalization may be accomplished or substantially accomplished via metal patterning in the back end processes. Further, preferably the invention is practiced on silicon on oxide (SOI) to reduce or minimize formation of parasitic transistor/path during circuit operation.
In an alternative embodiment of the invention, alternating P and N regions can be utilized as isolation regions rather than directly as active devices. In this case, leakage from circuit blocks of dissimilar conductivity type does not affect circuits in neighboring regions.
It may be noted that the present invention may be very useful as voltage thresholds (Vt's) are decreasing and critical geometries are decreasing, and, for these reasons, a simpler fabrication may be desirable as processing drives below ninety nanometers. Also, as channel thicknesses decrease, leakage may be mitigated to a point where the present invention is particularly valuable. The present invention may also reduce fabrication costs, since the fabrication process is simpler and supports generic (FE) precursors.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
The invention will now be described by reference to the accompanying figures. In these figures, various aspects of the structures have been shown and schematically represented in a simplified manner to more clearly describe and illustrate the invention. For example, the figures are not intended to be to scale. In addition, various aspects of the structures are illustrated as having particular shapes; however, as those skilled in the art will appreciate, the invention is not limited to constructions of any particular shape.
As mentioned above, this invention generally relates to integrated circuits or semiconductor structures or wafers.
Upper layer 14, in turn, includes N-type region 22, an array of P-type regions 24, and a multitude of space-charge regions 26. With the embodiment of structure 10 shown in FIGS. I and 2, upper layer 14 is comprised primarily of the N-type region 22, the P-type regions 24 are spaced apart in layer 14, and each of those P-type regions is surrounded by a respective one of the space-charge regions. 26. More specifically, with this embodiment, P-type regions 24 are uniformly spaced apart in an orthogonal grid pattern, including parallel rows and parallel columns, with the rows perpendicular to the columns.
Contacts 16 are provided to help connect together various areas of the N-region and various P-regions of layer 14. More particularly, a first set of the contacts are above and in electrical contact with specific areas of N-region 22, and a second set of the contacts are above and in electrical contact with P regions 24. With the arrangement shown in
The P— and N-regions of layer 14 may be connected together in a large number of ways to form many specific devices. For instance,
With reference again to
Semiconductor layer 14 may be formed by providing a suitable substrate, and then implanting N-type dopants to form N-region 22, and implanting P-type dopants to form P-regions 24. Contacts 16 may be affixed in place on top of the N-region and P-regions.
It may be noted that space-charge regions 26 are preferably formed naturally as the result of implanting the P-type dopants in regions 24. In particular, in this implantation process, the P-type dopants migrate into N-region 22 and form an isolation interface between a P-region and the surrounding N-region.
Any suitable dopants may be used to form the N— and P-regions; and for example, the N-type dopants may be phosphorous or arsenic ions, and the P-type dopants may be boron ions. Also, any suitable masking technique or other suitable targeted ion implantation process may be used to implant the N and P type dopants in the desired areas of layer 14.
The preferred embodiment of the invention has a number of important advantages, and can be provided with a number of additional features. For example, when making the logic array, front-end processes (e.g., implantation, active devices) are generic or substantially generic, some are common between multiple devices, and devices can be defined into specific types by hard-wire (netlist). Also, the active devices of the logic array may be PN junctions formed adjacent to one another so that their overlap regions form a space-charge region, thus isolating one device from another (in two or three dimensions).
In addition, in the preferred procedure for making the logic array, the front end devices can be formed over an entire wafer or regions of fixed or arbitrary geometry. Personalization may be accomplished or substantially accomplished via metal patterning in the back end processes. Further, preferably the invention is practiced on silicon on oxide (SOI) to reduce or minimize formation of parasitic transistor/path during circuit operation.
Moreover, the present invention may be very useful as voltage thresholds (Vt's) are decreasing and critical geometries are decreasing, and, for these reasons, a simpler fabrication may be desirable as processing drives below ninety nanometers. Also, as channel thicknesses decrease, leakage may be mitigated to a point where the present invention is particularly valuable. The present invention may also reduce fabrication costs, since the fabrication process is simpler and supports generic (FE) precursors.
While the present invention has been particularly described in conjunction with a specific preferred embodiment and other alternative embodiments, it is evident that numerous alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore intended that the appended claims embrace all such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
Claims
1. A programmable, random logic device array, comprising:
- a substrate;
- a semiconductor layer above the substrate, including i) a first region of a first semiconductor type, ii) an array of spaced apart second regions of a second semiconductor type, and iii) a plurality of space-charge regions, wherein each of the space charge regions extends around a respective one of said second regions and separates said one of the second regions from the first region of the semiconductor layer, and wherein each of the second regions is contiguous with and is surrounded by a respective one of the space-charge regions;
- a first set of contacts, each of the first set of contacts being above and in physical and electrical contact with a respective one area of said first region of the semiconductor layer; and
- a second set of contacts, each of the second set of contacts being above and in physical and electrical contact with a respective one of said second regions;
- said first and second sets of contact facilitating connecting together the said areas of the first region and said second regions of the semiconductor layer in various, programmable ways.
2. A logic device array according to claim 1, wherein said second regions are uniformly spaced apart.
3. A logic device array according to claim 2, wherein said second regions are spaced apart in a grid pattern having a plurality of rows and columns.
4. A logic device array according to claim 3, wherein said first set of contacts are located on the rows and columns of said grid pattern.
5. A logic device array according to claim 4, wherein four of the first set of contact are uniformly spaced around each of at least some of the second regions.
6. A logic device array according to claim 1, wherein said first semiconductor type is N type, and said second semiconductor type is P type.
7. A logic device array according to claim 1, wherein said first region includes a multitude of separate sub-regions.
8. A logic device according to claim 1, wherein each of the space-charge recgions include both N type ions and P type ions.
4026736 | May 31, 1977 | Lesk |
4794442 | December 27, 1988 | Warner, Jr. et al. |
4933736 | June 12, 1990 | Conner et al. |
5629537 | May 13, 1997 | Nagamatsu et al. |
6314540 | November 6, 2001 | Huott et al. |
6326221 | December 4, 2001 | Lee et al. |
6541804 | April 1, 2003 | Tihanyi |
6812516 | November 2, 2004 | Noble et al. |
6856542 | February 15, 2005 | Roy et al. |
Type: Grant
Filed: Aug 25, 2005
Date of Patent: Sep 2, 2008
Patent Publication Number: 20070045733
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Harsaran S. Bhatia (Hopewell Junction, NY), Eric Kline (Rochester, MN)
Primary Examiner: Thomas Dickey
Assistant Examiner: Fazli Erdem
Attorney: Scully, Scott, Murphy & Presser, P.C.
Application Number: 11/211,813
International Classification: H01L 27/12 (20060101);