Patents Examined by Thomas Magee
  • Patent number: 7098527
    Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: August 29, 2006
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Jerry M. Brooks
  • Patent number: 7015545
    Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: March 21, 2006
    Assignee: Broadcom Corporation
    Inventors: Thomas G. McKay, Stephen Allott
  • Patent number: 6979846
    Abstract: A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: December 27, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Ichiro Mizushima, Tsutomu Sato
  • Patent number: 6972437
    Abstract: Disclosed is an AlGaInN LED with improved external quantum efficiency, in which a chip employing the LED has a horizontal plane formed in a lozenge shape so that the amount of total reflection of light is reduced when the light generated from an active layer interposed between hetero-semiconductor layers with different band gaps is emitted to the outside. Since the horizontal plane of the LED is formed to have a lozenge shape so that the amount of total reflection of light generated in the LED is reduced, it is possible to maximize external quantum efficiency determined by the degree of emission of the light generated in the active layer. The cleaved plane of the LED coincides with the crystal orientation of a wafer made of GaN or sapphire, thus improving the yield of the LED when the LED is cut and produced.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: December 6, 2005
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang-Tae Kim
  • Patent number: 6958505
    Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: October 25, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Catherine Mallardeau, Pascale Mazoyer, Marc Piazza
  • Patent number: 6953995
    Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: October 11, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram, Alan G. Wood
  • Patent number: 6946696
    Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 20, 2005
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Guy M. Cohen, Meikei Ieong, Ronnen A. Roy, Paul Solomon, Min Yang
  • Patent number: 6939799
    Abstract: A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises polysilicon conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion of first or second type conductivity enhancing impurity received thereover. An insulative layer is formed over the gate. An opening is formed into the insulative layer to a conductive portion of the gate. Semiconductive material conductively doped with a conductivity enhancing impurity of a second type is formed within the opening in electrical connection with the conductive portion, with the conductive diffusion barrier layer of the gate being received between the semiconductive material of the gate and the semiconductive material within the opening. Other aspects are disclosed and claimed.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 6939762
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the P type impurity region 13b and the P type well 13 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: September 6, 2005
    Assignee: Fujitsu Limited
    Inventors: Hiroaki Tsugane, Hisakatsu Sato
  • Patent number: 6927455
    Abstract: A first insulator (710) having an opening within a central region (551) is formed on a main surface (61S) of an epitaxial layer (610). Then, p-type impurities are ion implanted through the opening of the first insulator (710) and then heat treatment is carried out, thereby to form a p base layer (621) in the main surface (61S). An insulating film is formed to fill in the opening and then etched back, thereby to form a second insulator (720) on a side surface (71W) of the first insulator (710). Under conditions where the second insulator (720) is present, n-type impurities are ion implanted through the opening and then heat treatment is carried out, thereby to form an n+ source layer (630) in the main surface (61S) of the p base layer (621).
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: August 9, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Atsushi Narazaki
  • Patent number: 6917112
    Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: July 12, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej Sandhu
  • Patent number: 6912146
    Abstract: An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: June 28, 2005
    Assignee: Ovonyx, Inc.
    Inventors: Manzur Gill, Tyler Lowrey
  • Patent number: 6906350
    Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain and extends into a doped channel layer of a first conductivity type. Regions of silicon carbide adjacent to the source and the drain extend between the source and the gate and the drain and the gate, respectively. The regions of silicon carbide have carrier concentrations that are greater than a carrier concentration of the doped channel layer and are spaced apart from the gate.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: June 14, 2005
    Assignee: Cree, Inc.
    Inventor: Saptharishi Sriram
  • Patent number: 6906384
    Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamada, Tsutomu Sato, Shinichi Nitta, Hajime Nagano, Ichiro Mizushima, Hisato Oyamatsu, Yoshihiro Minami, Shinji Miyano, Osamu Fujii
  • Patent number: 6900085
    Abstract: One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: May 31, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark T. Ramsbey, Michael Fliesler, Mark Randolph, Mimi Qian, Yu Sun
  • Patent number: 6897482
    Abstract: A transistor has a source electrode and a drain electrode formed with a predetermined interval secured in between on a semiconductor layer formed to perspectively overlap a gate electrode. The source and drain electrodes are each longer in their lengthwise direction than in their widthwise direction. The source electrode has a recessed portion formed therein to allow the tip portion of the drain electrode in. The semiconductor layer protrudes out of the gate electrode to form a portion that does not overlap the gate electrode but overlaps the source electrode and a portion that does not overlap the gate electrode but overlaps the drain electrode. Thus, the protruding portion that overlaps the source electrode and the protruding portion that overlaps the drain electrode are separated from each other by the gate electrode so as to be independent of each other.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: May 24, 2005
    Assignees: Sanyo Electric Co., Ltd., Tottori Sanyo Electric Co., Ltd.
    Inventors: Satoshi Morita, Osamu Kobayashi, Kohei Oda
  • Patent number: 6888224
    Abstract: Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Terence Lawrence Kane, Michael P. Tenney
  • Patent number: 6881998
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate including an active region and an isolating region provided so as to enclose the active region; a capacitance insulating film that is provided on the active region and has a boundary portion in contact with the isolating region; an upper electrode provided on the capacitance insulating film so as to be spaced away from the isolating region; an electrode pad provided on the isolating region; a lead conductive film provided over a part of the capacitance insulating film and a part of the isolating region for connecting the upper electrode and the electrode pad; and an interlayer insulating film provided over the substrate.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: April 19, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shinichi Imai
  • Patent number: 6873048
    Abstract: A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer first thickness; selectively removing the second metal layer overlying the first channel region; forming a third metal layer; establishing a first MOSFET with a gate work function responsive to the thicknesses of the first and third metal layer overlying the first channel region; and, establishing a second MOSFET, complementary to the first MOSFET, with a gate work function responsive to the combination of the thicknesses of the first, second, and third metal layers overlying the second channel region.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: March 29, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Wei Gao, John F. Conley, Jr., Yoshi Ono
  • Patent number: 6858944
    Abstract: A bonding pad suitable for use in wire bonding an integrated circuit includes an approximately rectangular metal pattern. The bonding pad has at least one slot or hole in it, located at or adjacent to at least one corner of the approximately rectangular metal pattern. The slot or hole provides peeling stress relief.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: February 22, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tai-Chun Huang, Tze-Liang Lee