Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a mold layer on the package substrate to cover the semiconductor chip, the mold layer having a first side surface and a first trench disposed at the first side surface, and the first trench extending from a top surface of the mold layer toward a bottom surface of the mold layer, an antenna pattern on the mold layer, and a first connection terminal filling the first trench. The antenna pattern is electrically connected to the package substrate through the first connection terminal.

Abstract: A semiconductor package includes a first substrate, a first bonding pad on the first substrate, a solder ball on the first bonding pad, and a blocking layer on the solder ball, wherein a thickness of the blocking layer varies in a direction away from the first substrate.

Abstract: A substrate manufacturing method, an embedded substrate and a semiconductor are disclosed. The method includes: manufacturing a first semi-finished substrate including first circuit layers and a first dielectric layer arranged in staggered and laminated manner; arranging a viscous material layer on the first circuit layer to form a device adhering area; adhering an embedded device on the device adhering area, a pin face of the embedded device facing away from the viscous material layer; laminating a second dielectric layer on the first circuit layer, which covers the viscous material layer and the embedded device; manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer, the first conductive pillar extending through the second dielectric layer and configured for connecting the second circuit layer with the first circuit layer, the second conductive pillar being configured for connecting the embedded device with the second circuit layer.

Abstract: A semiconductor device includes: a substrate; a plurality of dies attached to a first side of the substrate; a molding material on the first side of the substrate around the plurality of dies; a first redistribution structure on a second side of the substrate opposing the first side, where the first redistribution structure includes dielectric layers and conductive features in the dielectric layers, where the conductive features include conductive lines, vias, and dummy metal patterns isolated from the conductive lines and the vias; and conductive connectors attached to a first surface of the first redistribution structure facing away from the substrate.

Abstract: A display apparatus is disclosed that includes a substrate, a display element, a transistor, and a pad. The substrate includes a display area and a peripheral area. The display element is disposed on the display area. The transistor is electrically connected to the display element. The pad is disposed on the peripheral area and having a multilayered structure. The pad includes a pad metal layer, a first pad protective layer disposed on the pad metal layer, and a second pad protective layer interposed between the pad metal layer and the first pad protective layer. The second pad protective layer includes a different material from the first pad protective layer. The transistor includes a semiconductor layer disposed on the substrate, a gate electrode disposed on a gate insulating layer that covers the semiconductor layer, and a connection electrode arranged on an interlayer insulating layer covering the gate electrode.

Abstract: A method for manufacturing an image display device according to an embodiment includes: preparing a first substrate that includes a circuit element formed on a first surface of a substrate, a first wiring layer connected to the circuit element, and a first insulating film covering the circuit element and the first wiring layer; forming a graphene-including layer on the first insulating film; forming a semiconductor layer that includes a light-emitting layer on the graphene-including layer; forming a light-emitting element that includes a light-emitting surface on the graphene-including layer and includes a top surface at a side opposite to the light-emitting surface by patterning the semiconductor layer; forming a second insulating film covering the first insulating film, the graphene-including layer, and the light-emitting element; forming a first via extending through the first and second insulating films; and forming a second wiring layer on the second insulating film.

Abstract: A display device comprises conductive layers disposed on a substrate in different layers, a via layer on the conductive layers, a bank disposed on the via layer and defining a light emission area, bank patterns on the via layer and extended in a first direction, a first electrode on the bank patterns and extended in the first direction, and a second electrode disposed on the bank patterns and extended in the first direction, and light emitting elements on the first electrode and the second electrode. The bank patterns are spaced apart from each other. The first and second electrodes are spaced apart from each other. The bank and the bank patterns define an alignment area in which the light emitting elements are disposed. An area, in which two or more of the conductive layers overlap each other in a plan view is about 80% or more in the alignment area.

Abstract: Provided are semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a first base; a first semiconductor chip connected to the first base; a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure including a plurality of second semiconductor chips stacked in sequence in a first direction, the second semiconductor chip stack structure being provided with a plurality of first leads on an outermost side of the second semiconductor chips in the first direction, in which the first direction is a direction parallel to a plane of the first base; and at least one second base, signal lines in the at least one second base being connected to the first leads, the at least one second base being connected to the first base in a direction perpendicular to the plane of the first base.

Abstract: Aspects of the present disclosure generally relate to an MPS diode and a manufacturing method therefor. The MPS diode includes a semiconductor body including an active area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second conductivity type different from the first conductivity type, the plurality of wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The MPS diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the plurality of wells. A spacing between adjacently arranged wells increases in an outward direction from a center of the active area.

Abstract: The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, first sub-pixels and second sub-pixels. The first sub-pixels are disposed on the substrate. The first sub-pixels have a first orienting characteristic. A first adherent material is disposed between the first sub-pixels and the substrate. The second sub-pixels are disposed on the substrate. The second sub-pixels have a second orienting characteristic. A second adherent material is disposed between the second sub-pixels and the substrate. The first orienting characteristic and the second orienting characteristic are different. The first adherent material and the second adherent material are different.

Abstract: The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.

Abstract: A semiconductor package includes a buffer die, a first core die disposed on the buffer die, and a non-conductive film (NCF) disposed between the buffer die and the first core die so that the buffer die and the first core die are bonded to each other, wherein the NCF includes a dibenzocyclooctadiene (DBCOD)-based compound.

Abstract: A circuit module includes: a first circuit component having electrode pads on a first surface; and a second circuit component having electrode pads on a second surface. A conductive bonding material joins the electrode pads of the first circuit component to the electrode pads of the second circuit component respectively. A first reinforcing bonding material is not in contact with the conductive bonding material and joins the first surface of the first circuit component to the second surface of the second circuit component. A second reinforcing bonding material is located in contact with the first reinforcing bonding material, and joins the first surface of the first circuit component to the second surface of the second circuit component.

Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.

Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.

Abstract: A display module includes a display panel, an optical layer disposed on the display panel, an antireflection layer disposed on the optical layer, and the antireflection layer includes a first layer including silicon oxynitride, a second layer disposed on the first layer and including silicon nitride, and a third layer disposed on the second layer and including polysilazane.

Abstract: A 3D integrated structure and a method for fabricating the structure. In the method, a first trimming process is performed in a peripheral region of a wafer stack to form a chamfered surface adjacent to and surrounding an active device region. As a result, a thickness of the wafer stack along the chamfered surface gradually decreases from an edge of the active device region outward. In this way, a photoresist layer can be subsequently easily applied to cover the junction of the active device region and the chamfered surface, without the formation of discontinuities there, which may affect the subsequent processes. Additionally, in the method, a second trimming process is performed at an edge of the peripheral region to form a clamping surface adjacent to and surrounding the chamfered surface. In this way, it is unnecessary to clamp the wafer stack at a top surface thereof.

Abstract: Disclosed three-dimensional stacked package structure includes: a packaging substrate, having a substrate body, connecting leads, a through-hole penetrating the substrate body, a first pad and a second pad on opposite surfaces of the substrate body. The stacked structure on the first surface of the substrate body includes a second storage block, and a first storage block above the second storage block; the connecting leads include a first lead and a second lead with equal lengths, the first lead is above the package substrate, and one end is electrically connected to the first pad, and the other end is electrically connected to the first storage block. The second lead passes through the through-hole, and one end is electrically connected to the second storage block, the other end is electrically connected to the second pad. The present disclosure reduces the crosstalk between signal lines, thereby reducing signal delay between different storage blocks.

Abstract: An MPS diode and a manufacturing method is provided. The diode includes a semiconductor body including an active area and an adjacent termination area, the active area includes a drift region of a first conductivity type, and a plurality of wells of a second type different from the first conductivity type, the wells being mutually spaced apart, each well forming a respective PN-junction with the drift region. The diode further includes a metal layer assembly arranged on a surface of the semiconductor body and at least one metal layer, the metal layer assembly forming a plurality of Schottky contacts together with the drift region and a plurality of respective Ohmic contacts with the wells. The drift region includes a doped region surrounding each of the wells and having a higher dopant concentration than a remainder of the drift region, and the doped region is spaced apart from the termination area.