Abstract: A method of manufacturing a thin-film transistor TFT with a metal cross over structure includes: etching the first metal layer through a first patterned photoresist to form a gate electrode and a lower metal pattern; anodizing the first metal layer; removing the first patterned photoresist; depositing a semiconductor layer on the etched first metal layer; depositing a second metal layer on the semiconductor layer; anodizing the second metal layer through a second patterned photoresist to form an anodized segment; and etching the second metal layer through the second patterned photoresist to form first and second upper metal patterns, in which the first upper metal pattern has drain and source electrodes connected to the anodized segment and electrically isolated from each other by the anodized segment, and the second upper metal pattern forms a metal cross over structure with the lower metal pattern.

Abstract: A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the seco

Abstract: A display panel, a display screen, and a manufacturing method of a display screen are provided. The display panel includes a light-emitting assembly, a driving assembly, multiple first conductive members, and multiple second conductive members. The light-emitting assembly includes multiple light-emitting units, where each of the multiple light-emitting units includes a first electrode and a second electrode spaced apart from the first electrode, and the first electrode surrounds the second electrode. The driving assembly includes multiple driving units, where one of the multiple driving units is disposed in correspondence with one of the multiple light-emitting units, and different driving units correspond to different light-emitting units. Each of the multiple driving units includes a third electrode and a fourth electrode spaced apart from the third electrode, and the third electrode surrounds the fourth electrode.

Abstract: A display device includes a display panel including first and second areas each including a plurality of element areas and a peripheral area, a first light blocking pattern disposed on the display panel and overlapping the second area, and a second light blocking pattern disposed on the display panel, overlapping the second area, and disposed farther away from the display panel than the first light blocking pattern. Each of first, second and third element areas of the second area includes a plurality of light emitting areas and a non-light-emitting area disposed between the light emitting areas, the first light blocking pattern overlaps the non-light-emitting area of the second element area, and the second light blocking pattern overlaps the non-light-emitting area of the first element area and the non-light-emitting area of the third element area.

Abstract: A method of fabricating a semiconductor device may use, as an internal contact region, a region in which a memory cell region overlaps a core and/or peripheral region by bonding at least a partial region of the memory cell region to at least a partial region of the core and/or peripheral region by a direct bonding method, and thus, even when an additional contact region is secured outside the memory cell region to be smaller, signals and/or power may be transmitted between the memory cell region and the core and/or peripheral region.

Abstract: A display device includes: a circuit substrate including a plurality of pixel circuit units and a plurality of pads on a first surface thereof, the plurality of pads being electrically connected to the pixel circuit units; a display substrate on the circuit substrate and including a plurality of light emitting elements electrically connected to the pixel circuit units; a circuit board on the circuit substrate and including a plurality of circuit board pads electrically connected to the pads; a heat dissipation substrate on a second surface of the circuit substrate, the second surface being opposite to the first surface; and a cover substrate on the heat dissipation substrate and partially overlapping the circuit substrate and the circuit board. Each of the plurality of pads is in direct contact with at least one of the plurality of circuit board pads.

Abstract: A display panel and a display device are provided. The display device includes a display panel. The display panel includes a photosensitive area, a transition area, and a display area. The display panel further includes a base substrate, a drive circuit layer, and a light-emitting layer. By disconnecting the light-emitting layer in an opening on the base substrate, a lateral intrusion path from a through-hole in the photosensitive area to the display area for water and oxygen can be blocked. Therefore, poor display such as black hole spots caused by water and oxygen intrusion can be solved.

Abstract: A semiconductor module includes a substrate, a semiconductor element and a heat sink plate. The substrate is included in a circuit board. The semiconductor element is disposed at the heat sink plate inside the substrate. A fluid is sealed inside the heat sink plate.

Abstract: An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

Abstract: The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer comprises tantalum, and the assisting blocking layer comprises copper manganese alloy.

Abstract: A method of manufacturing a decorative sheet includes a step of stacking a light-shielding film and a design film on a surface of a base material film and a step of removing a part of the light-shielding film and a part of the design film by radiating laser light from positions on the base material film and forming transparent portions. The design film the part of which is removed forms a design layer that displays design. The light-shielding film the part of which is removed forms a light-shielding layer that covers the design layer.

Abstract: Three-dimensional memory devices and fabricating methods therefore are disclosed. The memory device can comprise a stack structure comprising a plurality of gate layers, a plurality of first insulating layers, and a plurality of second insulating layers. The stack structure has a staircase region comprising a plurality of stair structures. Each stair structure comprises a first portion of the stair structure comprising one gate layer and a first portion of one first insulating layer, and a second portion of the stair structure comprising a second portion of the one first insulating layer and a second insulating layer. The memory device can further comprise at least one contact structure each located on a top surface of one of the plurality of stair structures, and at least one contact portion in contact with the at least one contact structure.

Abstract: A display panel and a display device are provided. The display panel includes a pixel definition layer and an encapsulation layer. The pixel definition layer is provided with a plurality of concave portions, the encapsulation layer is provided on the pixel definition layer, the encapsulation layer is provided with a plurality of convex portions, and the convex portions and the concave portions are fitted with each other to form an interlocking structure, so as to improve an adhesion between the encapsulation layer and the pixel definition layer. Therefore, a risk of film debonding and separation among the encapsulation layer, the pixel definition layer, and the functional layer is reduced.

Abstract: A display panel includes a substrate including a display area and a pad area spaced apart from the display area, and an uneven pad disposed on the substrate in the pad area. The uneven pad includes a first conductive layer, a first organic layer disposed on the first conductive layer and having an upper surface having an uneven shape, and a second conductive layer disposed on the first organic layer.

Abstract: The present invention relates to a method of manufacturing a backside illumination (BSI) CMOS optical sensor and more specifically to a method of reducing the cross talk and enhance the photon detection efficiency (PDE) in a backside illumination (BSI) CMOS optical sensor. In particular the claimed method comprises the step of creating an isolation structure between the adjacent sensing elements of the pixel-array of said BSI CMOS optical sensor, so as to isolate all the adjacent sensing elements from each other, and the step of creating a common voltage backside applying structure to all the sensing elements of said pixel-array, so as to connect all the sensing elements to a common voltage bias.

Abstract: An electronic apparatus comprises a semiconductor device and a mounting substrate. The semiconductor device includes a semiconductor chip and a wiring circuit board. The chip includes a circuit blocks and first electrode pads. The wiring circuit board includes a first surface and a second surface. The first surface includes second electrode pads wirings. The second surface includes ball electrodes. A first wiring supplies a ground potential to a first circuit block. A second wiring supplies a ground potential to a second circuit block. The second surface includes a first extension pad and a second extension pad. The first extension pad and the second extension pad are disposed at positions at which they are connected to each other on the second surface side through a single ball electrode.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.

Abstract: A method of producing a light emitting diode (LED) array comprises: forming a semiconductor layer of group III nitride material; forming a dielectric mask layer over the semiconductor layer, the dielectric mask layer having an array of holes through it each exposing an area of the semiconductor layer; and growing an LED structure in each of the holes. The array of holes comprises a first set of holes each having a first cross sectional area and a second set of holes each having a second cross sectional area different from the first cross sectional area.

Abstract: A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.

Abstract: A display device includes a substrate. A thin-film transistor layer includes a transistor disposed on the substrate. A via layer is disposed on the transistor. A light-emitting element layer is disposed on the thin-film transistor layer. The light-emitting element layer Includes a pixel defining layer and a spacer disposed thereon. An encapsulation layer is disposed on the light-emitting element layer. An insulating layer is disposed on the encapsulation layer. A touch line is disposed on the insulating layer. A dam is disposed in a non-display area and surrounds a display area. An outer via is disposed beyond the dam. The outer via and the via layer are on the same layer. The encapsulation layer covers one end of the outer via facing the display area. The insulating layer covers a top surface of a portion of the outer via adjacent to an edge of the encapsulation layer.