Patents Examined by Tiberiu Dan Onuta
  • Patent number: 12058861
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Patent number: 12051705
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 30, 2024
    Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres Bianchi, Marios Barlas, Alexandre Lopez, Bastien Mamdy, Bruce Rae, Isobel Nicholson
  • Patent number: 12033934
    Abstract: A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: July 9, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Yu-Ying Lee
  • Patent number: 12027590
    Abstract: A silicon carbide semiconductor device includes a drift layer of n-type formed on a semiconductor substrate composed of silicon carbide, a well region of p-type formed on a surface portion of the drift layer, a source region of p-type formed on a surface portion of the well region, a gate insulating film formed in contact with the source region, the well region, and the drift layer, and a gate electrode formed on the gate insulating film. In the silicon carbide semiconductor device, oxygen is contained in a region having a predetermined thickness from an interface between the well region and the gate insulating film toward the well regions side.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 2, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Munetaka Noguchi
  • Patent number: 12029097
    Abstract: The present disclosure provides a display panel, a method for manufacturing the display panel, and a display device. The display panel includes: a light-emitting module including an electroluminescent element and a thin film encapsulation layer for encapsulating the electroluminescent element arranged on a first substrate sequentially; a quantum dot module including a plurality of quantum dot light-emitting units spaced apart from each other; and a second substrate located between the light-emitting module and the quantum dot module, and configured to support the quantum dot module at a side of the light-emitting module away from the first substrate. An orthogonal projection of the thin film encapsulation layer onto the first substrate is located within an orthogonal projection of the second substrate onto the first substrate.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: July 2, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Kai Sui, Jingkai Ni, Zhongyuan Sun, Qian Jin