Patents Examined by Tien Mai
  • Patent number: 8427796
    Abstract: Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 23, 2013
    Assignee: QUALCOMM, Incorporated
    Inventors: Eugene R. Worley, ByungWook Min, Der-woei Wu
  • Patent number: 8416547
    Abstract: Described herein is technology for, among other things, short-circuit protection. The technology involves sensing a current that is based on an output current and generating a current sense signal in response. The technology further involves buffering the current sense signal. The technology further involves limiting the output current when it exceeds a threshold value.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: April 9, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Kwok-Fu Chiu
  • Patent number: 8400750
    Abstract: A particle charger with sheath air flow for enhancing charging efficiency includes a housing and a discharge wire. The housing has a charging chamber for accommodating the discharge wire, a particle inlet, a sheath air inlet, an outlet and an accelerating channel. A clean sheath air is guided through the sheath air inlet into the charging chamber to surround charged particles, reducing deposition of charged particles on the inside wall of the housing. A relatively small annular gap of accelerating channel accelerates the charged particles to exit the particle charger, and therefore minimized the particle electrostatic loss due to depositing on the inner surface of the housing. Additionally, uncharged particles approach the discharge wire axially, and charged particles move away radially. It is helpful for the charged particles to diffuse rapidly and uniformly, thereby enhancing the charging efficiency.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: March 19, 2013
    Assignee: National Chiao Tung University
    Inventors: Chuen-Jinn Tsai, Lin Guan-Yu, Chen Hui-Lin
  • Patent number: 8400742
    Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current mirror is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Wei Lai, Wade Ma
  • Patent number: 8390969
    Abstract: The present invention provides a smoke-free ESD protection structure used in integrated circuit devices. A JFET or n-channel MOS transistor is coupled between an I/O pad, and a transistor and diode, wherein the JFET or n-channel MOS transistor limits the current flowing through the diode and transistor to prevent the integrated circuit device from heating up and catching on fire or smoke during the smoke test. Moreover, the integrated circuit device will not be damaged by the smoke test.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventor: James Nguyen
  • Patent number: 8379363
    Abstract: A bulk erase tool to erase a perpendicular media recording (PMR) disk of a disk drive is disclosed. The bulk erase tool comprises a housing to receive a disk drive and at least one of a first pair of magnets mounted in the housing to be positioned above the received disk drive to provide a magnetic field to erase the top side of the disk and a second pair of magnets mounted in the housing to be positioned below the disk drive to provide a magnetic field to erase the bottom side of the disk.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: February 19, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Pusphanathan Kolunthavelu, Anandan Vengadasalam
  • Patent number: 8369053
    Abstract: A protection circuit apparatus comprises an electrostatic discharge circuit coupled to an isolation filter. The isolation filter comprises an inductor coupled to a ground-coupled capacitor, the inductor and the capacitor being coupled to the electrostatic discharge circuit. The inductor is also coupled to an electrostatic discharge sensitive device to be protected from an electrostatic discharge event.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: February 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xavier Moronval, Cedric Cassan, Jeffrey Jones, Olivier Lembeye
  • Patent number: 8358112
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: January 22, 2013
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Fabrice Paillet, Tanay Karnik, Vivek De
  • Patent number: 8345395
    Abstract: The present invention describes an electrostatic discharge protection circuit that protects an internal circuit of a semiconductor device from electrostatic discharge. The electrostatic discharge protection circuit includes a first electrostatic protection unit that transfers static electricity as a driving signal and also discharges the static electricity to a first discharge line when the static electricity is generated in a pad. It also includes a second electrostatic protection unit that discharges the static electricity generated in the pad to a second discharge line in response to the driving signal transferred from the first electrostatic protection unit. Since the first electrostatic protection unit performs an electrostatic discharge operation and at the same time aids the driving of the second electrostatic protection unit, electrostatic discharge performance can be enhanced while a layout area of the electrostatic discharge protection circuit can be reduced.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Jeong Son
  • Patent number: 8339757
    Abstract: An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: December 25, 2012
    Assignee: Faraday Technology Corp.
    Inventors: Fu-Yi Tsai, Ming-Dou Ker
  • Patent number: 8320091
    Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 27, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Colin McHugh
  • Patent number: 8289030
    Abstract: A system is used with a plurality of modules, each module requiring galvanic isolation from the other modules. Galvanic isolators are employed, each having an input and an output, the output galvanically isolated from the input, the output responsive to the input according to a response characteristic of the isolator. Each module has, a respective first isolator and a respective second isolator. The input of each respective first isolator and each respective second isolator for each module is disposed controllably to receive an activation signal from the module indicative of a module fault to be annunciated or to receive a test signal from the module, the test signal being smaller than the activation signal. The outputs of the respective first isolators are aggregated to a first node and the outputs of the respective second isolators are aggregated to a second node.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: October 16, 2012
    Assignee: Sendyne Corporation
    Inventor: Victor Marten
  • Patent number: 8289672
    Abstract: The present invention concerns a method of producing a lightning diverter for conducting a lightning-induced electrical current, which is to be placed on structures such as wings on wind turbines, aircraft components, radomes and the like with the purpose of lightning protection. The method comprises the steps of making a plurality of holes in a plate of an electrically conductive material, filling said holes at least partly with one or more electrically non-conductive materials, and then finally dividing the plate—preferably into strips. The lightning diverter obtained hereby consists of a layer of electrically non-conductive material with a plurality of isolated segments of electrically conductive material. The invention further relates to a diverter strip with isolated segments of concave shapes being advantageous because of the good connection between the segments and the non-conductive material.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: October 16, 2012
    Assignee: LM Glasfiber A/S
    Inventors: Morten Dahl, Lars Tilsted Lilleheden, Lars Bo Hansen
  • Patent number: 8289668
    Abstract: Current differential protection with charging current compensation is provided for a power apparatus, such as a power transmission line. Individual terminals dynamically determine their respective contributions, if any, to the charging current compensation value as availability of one or more voltage sources dynamically changes within the power apparatus. Respective terminals calculate local contributions to a charging current compensation value based on local voltage measurements. A loss of a voltage source is handled by adjusting multipliers for the remaining compensation points to reflect the total charging current. A local contribution is suppressed when the local voltage source is no longer available. After applying the local contributions, an alpha plane analysis may be used to determine when to trip the power apparatus.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: October 16, 2012
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Bogdan Z. Kasztenny, Normann Fischer
  • Patent number: 8279573
    Abstract: A circuit protection device for protection of circuitry is provided. The circuit protection device comprises a housing defining a chamber and a plurality of conductors. The conductors are configured to connect to the circuitry and extending into the chamber, and comprise at least a first conductor and a second conductor spatially separated from the first conductor. The circuit protection device further comprises an ignition component disposed in the chamber and configured to electrically connect the first and second conductors. A circuit protection system is also presented.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: October 2, 2012
    Assignee: General Electric Company
    Inventors: Juntao Wu, John Thomas Garrity, Chun Cheryl Zhan
  • Patent number: 8264804
    Abstract: A device for preventing the explosion of an element of an electrical transformer provided with a tank containing a combustible cooling fluid, comprising a pressure release element for decompressing the tank, and a bag placed downstream of the pressure release element and configured to pass from a flat state to an inflated state upon the rupture of the pressure release element and for confining fluid.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: September 11, 2012
  • Patent number: 8264812
    Abstract: A substrate-chucking electrostatic chuck (ESC) is disclosed which is sub-divided into at least three groups of electrostatic blocks, to uniformly chuck the substrate. A substrate bonding apparatus and method for a liquid crystal display (LCD) panel using the electrostatic chuck is also disclosed. The ESC includes at least three groups of electrostatic blocks which chuck the substrate using electrostatic chucking forces respectively generated by different voltages applied to the electrostatic blocks in association with the electrostatic block groups, and release the chucked substrate when the voltages are cut off.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 11, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Jong Won Kim
  • Patent number: 8243404
    Abstract: An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 14, 2012
    Assignee: Faraday Technology Corp.
    Inventors: Ming-Dou Ker, Chun-Yu Lin, Fu-Yi Tsai
  • Patent number: 8243411
    Abstract: A method for identifying a type of fault condition in a circuit breaker includes monitoring a branch circuit for a fault condition. In response to detecting the fault condition, interrupting current flow through the branch circuit. The type of fault condition is stored in a memory device from which it is retrieved in response to receiving a control signal. The type of fault condition is indicated based on the mechanical position of a circuit breaker handle as a function of time.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: August 14, 2012
    Assignee: Schneider Electric USA, Inc.
    Inventor: Brett Larson
  • Patent number: 8228653
    Abstract: An electronic control for a circuit breaker with automatic breaker rating is disclosed. The electronic control includes a memory to store circuit breaker ratings, a breaker rating switch to select circuit breaker ratings, and a microprocessor operatively coupled to the breaker rating switch and the memory. The microprocessor is configured to interpret a selected circuit breaker rating of the breaker rating switch, set an amplifier gain adjustment for the circuit breaker based on the selected circuit breaker rating, and transmit the selected circuit breaker rating to the memory for storage in the memory.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: July 24, 2012
    Assignee: General Electric Company
    Inventors: Nataniel Barbosa Vicente, Sreenivasulu Reddy Devarapalli, Todd Elliott Greenwood, Zubair Hameed, Brian Patrick Lenhart, Jr., Stephen James West