Patents Examined by Tifney L Skyles
  • Patent number: 8637970
    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: January 28, 2014
    Inventors: Chia-Lun Tsai, Chia-Ming Cheng, Long-Sheng Yeou
  • Patent number: 8623753
    Abstract: A method of forming a stackable protruding via package including enclosing an electronic component and electrically conductive first traces on a first surface of a substrate in a package body. Protruding via apertures are formed through the package body to expose the first traces. The protruding via apertures are filled with solder to form electrically conductive vias in direct physical and electrical contact with the first traces. Via extension bumps are attached to first surfaces of the vias. The vias and the via extension bumps are reflowed to form protruding vias. The protruding vias extend from the first traces through the package body and protrude above a principal surface of the package body. The protruding vias enable electrical connection of the stackable protruding via package to a larger substrate such as a printed circuit motherboard. Further, the protruding vias in accordance with one embodiment are formed with a minimum pitch.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: January 7, 2014
    Inventors: Akito Yoshida, Mahmoud Dreiza, Curtis Michael Zwenger
  • Patent number: 8597969
    Abstract: In an optical semiconductor device including a semiconductor laminated body including at least a light emitting layer, a first metal body including at least one first metal layer formed on the semiconductor laminated body, a support substrate, a second metal body including at least one second metal layer formed on the support substrate, and at least one adhesive layer formed in a surface side of at least one of the first and second metal bodies, the semiconductor laminated body is coupled to the support substrate by applying a pressure-welding bonding process upon the adhesive layer to form a eutectic alloy layer between the first and second metal bodies. At least one of the first and second metal layers has a triple structure formed by two tight portions and a coarse portion sandwiched by the tight portions.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: December 3, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Noriko Nihei, Shinichi Tanaka, Yusuke Yokobayashi
  • Patent number: 8598700
    Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Matthew Nowak, Thomas R. Toms
  • Patent number: 8552521
    Abstract: A semiconductor package removes power noise by using a ground impedance. The semiconductor package includes an analog circuit block, a digital circuit block, an analog ground impedance structure, a digital ground impedance structure, and an integrated ground. The integrated ground and the analog circuit block are electrically connected via the analog ground impedance structure, and the integrated ground and the digital circuit block are electrically connected via the digital ground impedance structure, and an inductance of the analog ground impedance structure is greater than an inductance of the digital ground impedance structure.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: October 8, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Eun-seok Song, Hee-seok Lee, Sung-woo Park
  • Patent number: 8525254
    Abstract: A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: September 3, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Treu, Ralf Siemieniec
  • Patent number: 8513678
    Abstract: A light-emitting device includes a pixel having a transistor provided over a substrate, and a light-emitting element. The transistor includes a single-crystal semiconductor layer which forms a channel formation region, a silicon oxide layer is provided between the substrate and the single-crystal semiconductor layer, a source or a drain of the transistor is electrically connected to an electrode of the light-emitting element, and the transistor is operated in a saturation region when the light-emitting element emits light. Further, in the light-emitting device, a gray scale of the light-emitting element is displayed by changing a potential applied to the gate of the transistor.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8472639
    Abstract: A microphone arrangement includes multiple pressure gradient transducers having an acoustic center, a first sound inlet opening leading to a front of a diaphragm, and a second sound inlet opening leading the back of the diaphragm. A directional characteristic of the pressure gradient transducers includes an omni portion and a figure-eight portion. The pressure gradient transducers have a direction of maximum sensitivity in a main direction. Each main direction of the pressure gradient transducers is inclined. The acoustic center of a pressure transducer and the pressure gradient transducers are positioned within an imaginary sphere having a radius that corresponds to double the largest dimension of the diaphragm of one of the transducers.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: June 25, 2013
    Assignee: AKG Acoustics GmbH
    Inventor: Friedrich Reining
  • Patent number: 8445896
    Abstract: The present invention discloses an organic light-emitting diode (OLED) device with high color rendering comprising a base plate, a first conductive layer, a plurality of white light emitting layers, and a second conductive layer, wherein the spectra of the white light emitting layers possess characteristics of complementarities so as to enhance the color rendering of the emitted white light, and at least one carrier regulating layer is selectively disposed between every two white light emitting layers so as to increase the emitting efficiency and color rendering.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 21, 2013
    Assignee: National Tsing Hua University
    Inventors: Jwo-Huei Jou, Chun-Jen Lin
  • Patent number: 8421182
    Abstract: A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 16, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Takehiko Nomura, Seikoh Yoshida, Sadahiro Kato
  • Patent number: 8030708
    Abstract: The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type well through respective gate insulating films. Two extension portions are formed from two first epitaxial growth layers which contact regions, of the P-type well and the N-type well, where channels are to be formed, respectively, and which are at a distance from each other. Two second epitaxial growth layers are formed on the first epitaxial growth layers in positions which are further at a distance from facing ends of the two extension portions in a direction of being separate from each other. Thus, two source/drain regions are formed on a PMOS side and on an NMOS side each. In the case of this structure, there is adopted no ion implantation for introducing impurities into a deep portion.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventor: Yasushi Tateshita
  • Patent number: 8008711
    Abstract: A p-type base layer shaped like a well is formed for each of IGBT cells, and a p+-type collector layer and an n+-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the p-type base layer. The p-type base layer of each of the IGBT cells includes a flat region including an emitter region and a bottom surface penetrated by a main trench, and first and second side diffusion regions between which the flat region is interposed. The first side diffusion region is situated just above the n+-type cathode layer and each of the bottom surfaces of the side diffusion regions forms a parabola-shaped smooth curve in longitudinal section. By replacing the p+-type collector layer with the n+-type cathode layer, it is possible to apply features of the above structure to a power MOSFET.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: August 30, 2011
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideki Takahashi
  • Patent number: 7999375
    Abstract: An electronic device can comprise a semiconductor die on which can be formed a micromechanical system. The micromechanical system can comprise a plurality of electrically conductive elongate, contact structures, which can be disposed on input and/or output terminals of the semiconductor die. The micromechanical system can also comprise a cooling structure disposed on the semiconductor die.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: August 16, 2011
    Assignee: FormFactor, Inc.
    Inventors: Eric D. Hobbs, Gaetan L. Mathieu
  • Patent number: 7994601
    Abstract: The present invention provides a semiconductor light receiving device that prevents local heat generation, has high-speed, high-sensitivity characteristics even at the time of an intensive light input, and exhibits high resistance to light inputs. The semiconductor light receiving device includes light absorption layers (3, 4) formed on an InP semiconductor substrate (1) wherein a buffer layer (21) containing a quaternary compositional material is formed between the InP semiconductor substrate (1) and the light absorption layers (3, 4).
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 9, 2011
    Assignee: NEC Corporation
    Inventor: Takeshi Nakata
  • Patent number: 7902561
    Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 8, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7868462
    Abstract: A semiconductor package comprises a package board and a plurality of semiconductor chips sequentially stacked on the package board. Each of the semiconductor chips comprises a semiconductor substrate and an open loop-shaped chip line formed on the semiconductor substrate. The open loop-shaped chip line has first and second end portions. The first and second end portions of the open loop-shaped chip lines are electrically connected to each other by connectors, and the connectors and the open loop-shaped chip lines constitute a spiral antenna.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seok Choi, Hee-Seok Lee
  • Patent number: 7856045
    Abstract: A surface emitting semiconductor component (1) with an emission direction which comprises a semiconductor body (2). The semiconductor body comprises a plurality of active regions (4a, 4b) which are suitable for the generation of radiation and are arranged in a manner spaced apart from one another, a frequency-selective element (6) being formed in the semiconductor body.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: December 21, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Marc Philippens, Tony Albrecht, Martin Müller, Wolfgang Schmid
  • Patent number: 7851830
    Abstract: A multigate Schottky diode comprising an electrically conducting active semiconductor region; first and second electrically connected metallic contact arms on the active semiconductor region forming ohmic contacts therewith; the ohmic contacts being spaced apart on the active semiconductor region to define a gate receiving channel therebetween. a plurality of electrically connected metallic gate fingers, the metallic gate fingers being in contact with the active semiconductor region to form Schottky junctions, the Schottky junctions being spaced apart on the active semiconductor region and extending at least partially along the gate receiving channel.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: December 14, 2010
    Assignee: RFMD (UK) Limited
    Inventors: Ronald Arnold, Dennis Michael Brookbanks
  • Patent number: 7847313
    Abstract: A group III-V nitride-based semiconductor substrate is formed of a group III-V nitride-based semiconductor single crystal containing an n-type impurity. The single crystal has a periodical change in concentration of the n-type impurity in a thickness direction of the substrate. The periodical change has a minimum value in concentration of the n-type impurity not less than 5×1017 cm?3 at an arbitrary point in plane of the substrate.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: December 7, 2010
    Assignee: Hitachi Cable, Ltd.
    Inventor: Masatomo Shibata
  • Patent number: 7847377
    Abstract: A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: December 7, 2010
    Inventors: Fumiyuki Osanai, Mitsuaki Katagiri, Satoshi Isa