Abstract: The present invention provides a technique which can make an image quality on a screen of a TFT liquid crystal display device uniform. A liquid crystal display device includes a TFT substrate on which TFT circuits are arranged in an array, a counter substrate which is arranged to face a surface of the TFT substrate on which the TFTs are formed, and a liquid crystal material which is filled between the TFT substrate and the counter substrate, wherein in the TFT substrate, assuming a film thickness and a width of a conductive film of the gate electrode lines in a first region thereof as GLD1 and GLW1 respectively, and a film thickness and a width of a conductive film of the gate electrode lines in a second region thereof which differs from the first region as GLD2 and GLW2 respectively, when the relationship GLD1<GLD2 is established, the relationship GLW1>GLW2 is established.

Abstract: A semiconductor device includes a GaN-based semiconductor layer that is formed on a substrate and an opening region, an electron conduction layer formed on an inner surface of the opening region, an electron supply layer that has a larger band gap than the electron conduction layer and is formed on the electron conduction layer disposed on the inner surface of the opening region, and a gate electrode formed on a side surface of the electron supply layer in the opening region. A source electrode is formed on the GaN-based semiconductor layer. A drain electrode is connected to a surface of the GaN-based semiconductor layer opposite to the source electrode.

Abstract: An image sensor and a method of fabricating the image sensor are provided. The image sensor includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type. The deep well is formed at a predetermined depth in the semiconductor substrate to divide the semiconductor substrate into a first conductivity type upper substrate area and a lower substrate area. The image sensor further includes a plurality of unit pixels integrating charges corresponding to incident light and comprising first conductivity type ion-implantation areas. The first conductivity type ion-implantation areas are separated from one another. Moreover, at least one unit pixel among the plurality of unit pixels further comprises the first conductivity type upper substrate area that is positioned under a first conductivity type ion-implantation area included in the unit pixel.

Abstract: A multi-layer composite electrode for a light-emitting device, comprising: a transparent, conductive layer; a reflective, conductive layer in electrical contact with the transparent, conductive layer; and a light-scattering layer formed between the transparent, conductive layer and the reflective, conductive layer over only a first portion of the transparent, conductive layer, wherein the light-scattering layer is relatively less conductive than the reflective, conductive layer and the reflective, conductive layer is in electrical contact with the transparent, conductive layer over a second portion of the transparent, conductive layer where the light-scattering layer is not formed. Also disclosed is a method of making such a multi-layer composite electrode in a light emitting device, and an organic light-emitting diode (OLED) device comprising such a composite electrode.

Abstract: A Resonant Cavity Light Emitting Diode (RCLED) device having a first active region having one or more quantum wells disposed within, a first chamber and a second chamber coupled to the first active region and a first reflector and a second reflector coupled to the first and second chambers respectively is disclosed. The RCLED can be optimized to emit radiation in the carbon-dioxide absorption band.

Abstract: An ultra high speed APD capable of realizing reduction in an operating voltage and quantum efficiency enhancement at the same time is provided. Under operating conditions APD, a doping concentration distribution of each light absorbing layer is determined so that a p-type light absorbing layer (16) maintains a p-type neutrality except a part thereof, and a low concentration light absorbing layer (15) is depleted. Moreover, a ratio between a layer thickness WAD of the p-type light absorbing layer (16) and a layer thickness WAD of the low concentration light absorbing layer (15) is determined so that WAD>0.3 ?m and a delay time of an element response accompanying a transit of carriers generated in the light absorbing layer by light absorption takes on a local minimum under a condition that a layer thickness WA (=WAN+WAD) of the light absorbing layer is constant.

Abstract: A color solid-state image sensing device comprising unit cells arranged two-dimensionally in a surface of a silicon substrate, each unit cell including a blue pixel provided as defined herein, a red pixel as defined herein and a green pixel as defined herein, wherein the relation P?W holds when W is a distance between the position of the center of gravity in a sensitivity distribution of the green pixel and the position of the center of gravity in a sensitivity distribution of the red pixel, and P is a pitch of arrangement of the unit cells.

Abstract: When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.

Abstract: A multi-channel thin film transistor structure including a first conducting layer, an insulating layer, a semiconductor layer and a second conducting layer is provided. The first conducting layer formed on a substrate includes a gate electrode. The insulating layer covers the first conducting layer. The semiconductor layer formed on the insulating layer includes a plurality of semiconductor islands located above the gate electrode. The second conducting layer formed on the insulating layer and on the semiconductor layer includes a source electrode and a drain electrode. Each one of the semiconductor islands is coupled electrically with the source electrode at one end and coupled electrically with the drain electrode at the other end.

Abstract: A thin film transistor includes a semiconductor pattern on a substrate, a gate insulating film to cover the semiconductor pattern, a gate electrode partially overlapping the semiconductor pattern with the gate insulating film there between, a hole in the gate electrode to expose the gate insulating film, an interlayer insulating film to cover the gate electrode, and a source electrode and a drain electrode contacting the semiconductor pattern through the interlayer insulating layer and the gate insulating layer, wherein the semiconductor pattern includes at least two channels between the source electrode and the drain electrode, the at least two channels having a region with a varying width.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A liquid crystal display panel including an active device array substrate, a second substrate, a sealant, and a liquid crystal layer is provided. The active device array substrate has a display area and a peripheral area surrounding the display area, and includes a first substrate, pixels, signal lines, floating lines, and a common circuit layer. The signal lines are electrically connected with the pixels. The floating lines are disposed in fan-out areas of the peripheral area. Each of the floating lines is aligned with one of the signal lines respectively. The common circuit layer is disposed on an area of the peripheral area outside the fan-out areas. An overall thickness of the floating line and the signal line aligned therewith is equal to a thickness of the common circuit layer. The sealant covers the floating lines, a part of the signal lines and the common circuit layer.

Abstract: A light emitting device includes: a plurality of transistors individually corresponding to a plurality of pixels arrayed in a matrix shape, and a plurality of wiring lines connected with the transistors and disposed between the pixels. The wiring lines include signal lines connected with the transistors of the pixel columns composed of a plurality of pixels along a row direction or a column direction, and two or more common electrode lines connected with the transistors of a pixel group composed of a plurality of pixels along the row direction and the column direction. The common electrode lines are arranged on the two sides centering the signal lines.

Abstract: An embodiment of the present invention relates to a method of manufacturing a flash memory device.