Abstract: There is disclosed a semiconductor device in which capacitor means are connected to multiple input terminals via latch means, and the terminals on one side of the capacitor means are commonly connected to the input of a sense amplifier, thereby attaining a reduction of the circuit scale, improvement of the operation speed, saving of the consumption power, reduction of the manufacturing cost, and improvement of the manufacturing yield.

Abstract: The present invention provides an technique for compensating a operation speed variation based on a principle that a circuit operation speed is adjusted by reflecting a delay time of an internal circuit itself that is an object of the operation speed fluctuation compensation.An internal circuit (1 in FIG. 1) has a critical path with an output terminal pair that outputs the identical logical values till its each operation is finished, and data in a complementary signal format as soon as its each operation is finished. A logical gate (2 in FIG. 1) can detect its operation end by sensing the signal transition into a complementary signal format at the output terminal pair of the internal circuit.

Abstract: A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.

Abstract: A semiconductor memory device includes a difference adjusting circuit for detecting difference in at least one of phase and frequency between an external clock signal and an internal clock signal, for outputting a control potential for reducing the difference, and a current control circuit for adjusting driving current of an internal clock signal generating circuit in accordance with an output potential from the difference adjusting circuit. The current control circuit includes a current change restricting circuit for making smaller an amount of change of current in the clock signal generating circuit with respect to the change in the output potential from the difference adjusting circuit. An internal power supply voltage obtained by lowering internally the external power supply voltage is applied to the clock signal generating circuit. Further, when supply of the external clock signal is stopped, the output potential from the difference adjusting circuit is held.

Abstract: Electronic circuit including an electronic power switch, for example an IGBT, controlled at its own gate terminal by resistive means in order to reduce its switching speed. The circuit includes a voltage sensor for reading a measurement that is a function of the potential of the collector of the electronic switch, for example its variation over time. The resistive means have a resistance that varies according to the command signal applied to an input terminal of the circuit and to the measurement read by the voltage sensor.

Abstract: A programmable delay line has delay elements that are responsive to at least one of two different calibration signals for varying their drive power characteristics and hence the delay period. Preferably, there are two sets of delay elements, responsive to a respective calibration signal, with one set comprising much fewer delay elements than the other set. The delay elements may be responsive to a digital calibration signal for discrete control, an analog calibration signal for continuous control, or both.

Abstract: A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

Abstract: A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

Abstract: A frequency divider or dual module prescaler having a division factor switchable between 1/N and 1/(N+1) with an input signal frequency of approximately 1 GHz. The divider includes only one input flip-flop to process the input signal and an intermediate signal having half the frequency as supplied to a divider expansion either directly, or in inverted.

Abstract: An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address and data buses to peripheral blocks. There is also provided a clock supply unit to supply clock signals in which at least one of the clock signals has a phase different from those of the remaining clock signals and the clock signals do not accomplish the setting operation at the same time.

Abstract: A semiconductor integrated circuit includes a first clock-input circuit receiving an external clock from an external source and outputting an internal clock, an output-control-clock generating circuit receiving the internal clock to generate an output-control clock, and a first data-output circuit outputting output data in synchronism with one of a rise timing and a fall timing of the output-control clock. The output-control-clock generating circuit controls a timing of the output-control clock such that the first data-output circuit outputs the output data a predetermined fraction of one clock cycle of the external clock after a clock pulse of the external clock.

Abstract: A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.

Abstract: A high precision charge pump used in a phase-lock loop incorporating a type-IV phase/frequency detector is designed and constructed to substantially eliminate the effects of ringing and glitch errors on the charge pump output current as averaged over a pump-up and pump-down cycle by the type-IV phase/frequency detector. The high precision charge pump is constructed exclusively of transistors of a single polarity (N-channels) that are so matched as to each have the same current characteristics. The current pulse length, absolute magnitude, and waveform envelopes of the charge pumps source and sink currents are defined by matched transistors. When the type-IV phase/frequency detector is operating in quasi flywheel mode, and no phase comparisons are being made, the charge pump's source current is equal to the sink current in all significant respects such that no incremental, residual charge is left on a loop capacitor following the conclusion of a sequential pump-up and pump-down sequence.

Abstract: An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.

Abstract: Correction of a duty-cycle is performed for use with a divide-by-two phase-splitter to increase precision of the duty-cycle of an incoming local oscillator signal in order to provide more precise phase relationships during generation of a phase and amplitude modulated carrier. Phase-splitter input signals are generated by limiting the slew-rate of an incoming signal to produce an intermediate signal. The intermediate signal is clipped in relation to a reference level. The reference level is adjusted by a feedback signal to produce an adjusted duty-cycle signal as an output signal. The feedback signal is proportional to the adjusted duty-cycle signal.

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: A circuit that includes at least two driver circuits. Each driver circuit receives analog information and drives a value related to the analog information to an analog bus. Each driver circuit also includes a select transistor to pass the value related to the analog information to the analog bus when the driver circuit is selected. The select transistor includes a source and a bulk. Each driver circuit further includes a bulk potential control circuit (BPCC) to couple the bulk to the source when the driver circuit is selected and to couple the bulk to a voltage supply when the driver circuit is not selected.

Abstract: A driver circuit for supplying an electric current to a device having a pair of power FET's connected in series between the device and a power supply.

Abstract: A driving circuit with low power consumption and high operational speed, and including transistors Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, P.sub.1 and P.sub.2, resistors R.sub.1 and R.sub.2, and diodes D.sub.1 and D.sub.2 which form a high-level feeding circuit for setting the output terminal level at the high level; and a constant-current source I.sub.BS, current mirror circuit MR.sub.12, transistors Q.sub.11, Q.sub.13 and Q.sub.14, resistor R.sub.11, and Schottky diode DS.sub.11 which form a low-level feeding circuit for setting the output terminal level at the low level. When the output terminal (T.sub.out) level is changed to the high level or low level, a large current flows into the base of transistor Q.sub.3 or Q.sub.13, and a rapid change takes place for the output terminal level. When the output terminal level reaches the prescribed voltage, the current flowing into the base of transistor Q.sub.3 or Q.sub.13 disappears.