Abstract: A novel waveform generating for generating a waveform having symmetrical rise and fall times. The waveform generator of the present invention includes a first current source, a second current source, a MOS capacitor and a clamping circuit. The first current source and the second current source are coupled to a node such that current generated by the first current source flows into the capacitor and current generated by the second current source flows out of the capacitor. The clamping circuit is also coupled to the node such that the output voltage generated by the waveform generator is limited to a minimum and a maximum value. Therefore, by controlling the current flowing into the node, and the capacitance at the node, the rate at which the output voltage changes over time is controlled. As such, a waveform having very precise rise and fall times is generated.

Abstract: In this invention is described a CMOS buffer that reduces short circuit current in the output stage. The short circuit current is a result of current flowing between circuit bias and ground through the output transistors during switching transition. The reduction in shorting current is accomplished by driving the two CMOS output transistors of opposite type separately, and providing a turn off signal for one output transistor ahead of the turn on signal for the other transistor. Thus one transistor is turned off before the other transistor is turned on, reducing shorting between the two transistors. The on and off signal delay is controlled from unbalanced inverters connected separately to each input of the output transistors.

Abstract: By setting the substrate potential of a transistor of a driver means lower than the substrate potential of a transistor of a bias means in an intermediate potential generation circuit which supplies a cell plate potential of a memory cell and a precharge potential of a bit line, a flow of a through current in a transistor of the driver means is prevented. Therefore, reduction of a power consumption of the device during standby can be realized.

Abstract: A structure is provided to create a voltage-independent capacitive structure using a typical MOS fabrication process. The capacitive structure includes two FET devices connected in series by having their source, drain, and body terminals all coupled together into a common node. A biasing circuit that includes a current generator and a current mirror biases the common node so that a constant capacitance is maintained across the gate terminals of the two serially connected FET devices, independent of the applied voltage.

Abstract: A charge transfer from signal voltage (U.sub.S) to integrating capacitance (C.sub.O) is accomplished by means of charge transfer capacitance (C.sub.i), an active element (T) and controllable switches (S.sub.61, S.sub.62, S.sub.63, S.sub.64). The operation of the circuit is additionally based on the fact that the charge transfer to the charge transfer capacitance (C.sub.i) is terminated when the transistor (T) is in a current-carrying state and that current flow is ensured by a constant-current element set. These features are combined preferably in such a way that the breaking current of charge transfer is equally great as previously said current of the constant-current element.

Abstract: An apparatus to remove from operation a decoupling capacitor connected to a power supply providing power to logic circuitry in an integrated circuit. One technique for doing so is to connect a fuse in series with a decoupling capacitor. The present invention amplifies current transmitting through the fuse in a positive feedback manner to force the fuse to blow sooner than would normally occur. Therefore, when the current through the decoupling capacitor is deemed unacceptable, the fuse current is increased until such a time that the fuse opens.

Abstract: An output driver for high speed integrated circuits includes a static driver portion and a transient driver portion. The static driver size can be adjusted to satisfy the minimal requirements for maintaining output DC voltage levels. The transient drivers include a feed-back control from the output voltage node. During a transition, the transient buffer control will sense the output level and feedback to turn off the transient driver whenever the output level rises/falls across the trip point. Accordingly the di/dt noise will drop quickly once the output has reached the trip point. The transient drivers can be larger to speed up switching speed. The buffer can use single power and ground pins or multiple power/ground pins.

Abstract: A half-bridge circuit where the transistors comprising the half-bridge are electronically interlocked--precluding cross-conduction; and high-side voltage generation and logic level translation are integral to the interlock mechanism.

Abstract: A voltage booster circuit including a pull-up capacitor connected to the supply line via a PMOS switching transistor. The other terminal of the pull-up capacitor is supplied with a pull-up voltage switching between a first value determining charging of the capacitor, and a second value higher than the first and determining pull-up of the capacitor. A negative voltage source presents an output connected to the control terminal of a switch transistor, and generates a negative voltage of a value lower than the first pull-up voltage value when charging the capacitor, so as to saturate the switch transistor and charge the capacitor to a voltage close to the supply voltage.

Abstract: A level conversion circuit comprises a first CMOS circuit connected between a high voltage (5 V: VDD) power supply and ground to receive an input signal IN1 having an amplitude between a low voltage (3 V: VCC) and a ground voltage (0 V), a second CMOS circuit connected between the 5 V power supply and ground to output an output signal OUT1 having an amplitude between 5 V and 0 V, and first and second intermediate circuits cross-connected between the first and second CMOS circuits. All MOS transistors constituting these circuits have the gate oxide films whose allowable breakdown voltage is lower than 5 V and higher than 3 V.

Abstract: A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost the voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an "H" level to an "L" level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor.

Abstract: A temperature compensated current source for driving a multi-vibrator (19) includes a voltage generator (10) that outputs a voltage that is proportional to absolute temperature (PTAT) and a resistor (12) for setting the current output by the voltage generator (10). The temperature coefficient of the resistor (12) is chosen such that any variations in the current supplied by the voltage generator (10) are compensated for to result in a current that has substantially no temperature variation. This current is mirrored to a current source (18) for driving the multi-vibrator (19). The voltage across the resistor (12) is a function of temperature, with the current being a function of the value of the resistor (12). The temperature coefficient of the resistor (12) is substantially equal to the temperature coefficient of the voltage generator (10) to yield a temperature coefficient of substantially 0 ppm/.degree. C. for the current.

Abstract: An all npn totem pole TTL output stage is provided with an active regulation circuit that continuously senses the voltage level at the output terminal and feeds it back to control the drive signal that is applied to the base of the bottom output transistor to switch the output state of the load quickly without wasting transient current and then scale back the drive signal during steady state operation to minimize wasted current. When the load is driven into its output low state, the active regulation initially holds the drive signal at a high level so that the load switches quickly. Once the output voltage has fallen low enough, the active regulation reduces the drive signal such that the bottom output transistor is held on the edge of conduction and does not saturate. In this state, the bottom output transistor pulls the output voltage down to approximately ground without conducting any appreciable amount of current.

Abstract: A circuit for power arbitration, low battery voltage detection, and the operation of battery backed circuitry for systems in which the system power supply voltage range overlaps that of a battery source. A voltage regulator is used to regulate the battery voltage so that the voltage range of the battery source is below the voltage range of the system supply. The regulator is based on a silicon-bandgap referenced methodology and consumes an insignificant amount of current so that the battery life is not appreciably affected. The regulator also has a smaller variation in its output voltage than the battery. A temperature and supply voltage compensated voltage is produced by the combination of a subthreshold current source, parasitic bipolar devices, and voltage buffering, and used to provide a voltage source for the battery backed circuitry of the system. The regulated voltage is set to a value lower than the system supply and serves as the battery supply input for the power arbitration circuitry.

Abstract: A high-voltage level shifter includes one or more complementary NMOS/PMOS series intermediate transistor pairs to divide the high-voltage supply range into two or more sub-ranges. The level shifter has a differential structure with complementary NMOS input transistors. Cross-coupled PMOS output transistors provide complementary outputs. The complementary NMOS/PMOS series intermediate transistor pairs separate the NMOS input transistor drains from the PMOS output transistor drains. In order to divide the high voltage range into h subranges, h-1 complementary NMOS/PMOS series intermediate transistor pairs are used each being biased by monotonically increasing fixed intermediate voltages. In a shared-bias embodiment, each complementary NMOS/PMOS series intermediate transistor pair is biased by a single corresponding intermediate voltage.