Abstract: A programmable digital device designed to perform a matched filtering opeion on arbitrary binary phase-coded signals. The technique is used in secure communication systems and for various radar and missile fuzing operations. The essential features minimize the component by the specific networks for the summing units containing unique combinations of digital components. The output is converted to sign-magnitude format.

Abstract: A data processing apparatus having preprogrammed functions for calculating interest rate dependent variables employs an interest rate mode designation command to enable operation in a selected one of a set of interest rate modes. In the preferred embodiment actuation of an AEC key advances the interest rate mode in a circularly sequential manner among annual percentage rate (sometimes referred to an annual nominal interest rate), annual effective interest rate and annual continuous interest rate. In the preferred embodiment actuation of a key sequence including a compute key and the AEC key enables conversion of an interest rate specified in a first mode into an interest rate specified in the next sequential mode. The data processing apparatus includes a means for outputting an indication of the current interest rate mode.

Abstract: In a sequence control apparatus using a microprocessor performing its processing of operation in terms of one word as the unit therefor, a change indicating signal from a process condition detecting or measuring instrument connected to an I/O unit is taken into the microprocessor in a form combined with predetermined pattern data. With the resulting composite data, the contents of those bits of an accumulator in the microprocessor which do not correspond to the change indicating signal can be optionally processed.

Abstract: A data-storage buffer transfers data signals with other units in relatively large blocks of data. Such large blocks storable in large address spaces are not always filled with meaningful data. To more efficiently use the data-storage space in the data-storage buffer, the allocatable unit or segment of the data buffer is made smaller than the data capacity of the large block. Each time a large block of data is to be written into the data buffer, a sufficient number of the segments for storing data of one large block is allocated for receiving the data. After the data of the one block is written into the data buffer, the allocated segments are examined; all of the allocated segments not storing data from the one large block are deallocated. The invention is particularly useful for data buffers acting as cached data storage for large-capacity direct-access storage devices (DASD) and are coupled to host processors programmed to operate with such DASD.

Abstract: A digital filter having a recursive portion and a non-recursive portion. The digital filter is implemented using pipelining techniques and parallel arithmetic and parallel arithmetic in both portions.

Abstract: A four member encoding set is disclosed which allows the construction of combinational monolithic multipliers with a significant reduction in the number of devices required. The reduced device and wire count in the present technique allows a multiplier circuit of any given size to be made less expensively or alternatively allows a larger precision multiplier to be constructed.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.

Abstract: The embodiment obtains rapid switching between system control programs (SCPs) by switching an address in a prefix register in a CPU of a MP or UP data processing system from a guest SCP's PSA (program save area) to a host SCP's PSA by fetching the host prefix value from a predetermined control block in main storage. The prefix register loading changes the control of the CPU from a preferred guest SCP to a host SCP. This SCP switching is done by hardware and/or microcode means in the CPU. It further detects preset states in the CPU that enable a rapid determination of which SCP is to handle a sensed event, permitting the guest SCP to immediately handle events predetermined to belong to the guest. This manner of CPU control obtains for a preferred guest SCP (such as MVS/370) operating under a host SCP (such as VM/370) nearly the efficiency of standalone execution on the CPU by the preferred guest SCP.

Abstract: A bus interchange circuit for use with a microprocessor. Timing, gating, sequencing and storage circuitry provide an interface between a microprocessor and external systems requesting control of the microprocessor's busses.

Abstract: In an apparatus for decoding a variable length code represented by a code tree, a decoding table memory is read out and the read out data is decided as to whether it is terminal or intermediate data. In the case of a terminal data, its decoded result information in the data is delivered out. In the case of an intermediate data, its data of the same number of bits as indicated by information of the data indicating the number of bits to be entered is entered from an input code train; this data and information of the intermediate data for determining an address of the decoding table memory to be accessed are added together to obtain the address of the memory to be accessed next; the address thus obtained is used to access the decoding table memory; and this operation is repeated until a terminal data is obtained.

Abstract: A system is disclosed for transferring words from an input source to a computer bus which can issue an acknowledge or a negative acknowledge signal. The system includes registers for storing the words to be transferred. It further includes control circuitry for initiating the transfer of a first word on the output bus, and, if negatively acknowledged, retrying the transfer. The control circuitry is further capable of initiating, before the retry, the transfer on the bus of another word or words received from the input source after the first word.

Abstract: A sampling frequency converter for converting a first signal sampled at a first sampling frequency f1 into a second signal sampled at a second sampling frequency f2 comprising an interpolation device supplied with the first signal, for inserting L-1 zeros (L is an integer) for every sampling time, a filter circuit for attenuating a frequency component over a frequency f/2 (f is a frequency) within an output signal of said interpolation device, where the filter circuit has a series circuit consisting of a finite impulse response digital filter and an infinite impulse response digital filter, and the frequency f is equal to the first sampling frequency f1 when f1<f2 and equal to the second sampling frequency f2 when f1>f2, and a decimation device for extracting every M-th (M is an integer) output signal of the filter circuit, to produce said second signal.

Abstract: A peripheral subsystem accepts and responds to a plurality of supervisory channel commands which alter the operation of the subsystem; i.e., logically partition, break the logical partition, adjust or amend the logical partition, ignore the logical partition, give operator controls for loading and unloading a record cartridge, suspending multipath reconnection and the like. These supervisory commands can be located anywhere in a I/O chaining sequence. Some of the supervisory commands will result in changes in the subsystem operation for the duration of the instant channel program or CCW chain while others persist for as long as the subsystem is operating or until a subsequent supervisory command overrides the previous supervisory command. One of the supervisory commands can selectively inhibit subsequent supervisory commands only within a given I/O chain. This selective inhibit provides subsystem integrity. At the end of the chain, the inhibition is removed.

Abstract: A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

Abstract: This circuit provides for extending a multiplexed address and data bus to remotely located computer peripheral devices. The present circuit eliminates skew of transmitted signals between microcomputers and their associated peripheral devices for lengths of up to one hundred feet. This circuit regenerates the bus timing for the peripheral device to accommodate the skew introduced by the length of cable and its associated drivers and receivers.

Abstract: An input/output bus structure for a computer system is disclosed in which the computer's central processor is fully protected from "foreign" I/O devices in that all of the incoming and outgoing bus signals are buffered and the buffer stores can be disabled under software control. To attach an input/output device on the input/output bus, certain requirements, both hardware and software, must be met. The input/output bus is enabled by writing a predetermined bit pattern to a preselected output port. In response to the bit pattern, hardware in the input/output port enables the input/output bus tranceivers to receive and send information.

Abstract: A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directions between the memory device and the input/output device independently of the CPU. A 2 m-bit bus is connected between the memory device and two m-bit buses connected to a bus switching circuit which controls the transfer of m-bit data words between the 2 m-bit bus and the register and the input/output device.

Abstract: Microprocessor apparatus for data exchange is controlled by information supplied via a microinstruction bus and a triggering line and transmits data from some external bidirectional data buses to other such buses. Data is supplied via data exchange units (1.sub.1, 1.sub.2, 2), internal bidirectional data buses and a switch. In addition to the transmission of information, the microprocessor apparatus can, depending on the code of the microinstruction, count the number of transmitted words via a counter and compare or mask data or arbitrate transmitted data via a data processing/converting unit. While executing microinstructions, the counter, the data processing unit, a register unit and a switch shape distinguishing features of the processed information, to be later fed to a conditional operation unit. The conditional operation unit shapes a generalized condition for readjustment of operation of a control unit.

Abstract: An arithmetic device having successive arithmetic registers connected in cascade, with buffer registers at each end of the cascade. An information exchange circuit bidirectionally connected to all the arithmetic registers for controlling information transfer therebetween such that the first register is connected to all of the other registers and every other register is also connected to a preceding and a succeeding register.

Abstract: A word processing system is provided having a bidirectional printer with formatting capability. The system includes a word processor having means for outputting a stream of sequential data readable in only one direction. The data comprises blocks of character data representative of the characters to be printed interspersed with blocks of control data representative of the format in which the characters are to be printed; each block of control data has an immediately preceding control block identifier. The bidirectional printer includes means for receiving the stream of sequential data, means for scanning the stream of data and means for inserting a control block identifier at the end of each control block which identifier corresponds to the identifier preceding the control block, whereby the stream of sequential data is made readable in both the forward and reverse directions within the printer.