Abstract: A read only memory system with replaceable units is provided in which the replacement units have a variable capacity. In addition, the system is sufficiently flexible so that a replacement unit substituted for an original unit may subsequently be removed from the system once and the original unit restored. The read only memory system has a fixed main read only memory with a plurality of addressable units of uniform capacity in combination with a substitute memory of a greater capacity than the addressable units. A control is provided with the capability of selectively disabling units of a fixed memory. It also can selectively enable a portion of the substitute memory and substitute the enabled portion for a disabled fixed memory unit. The control is also capable of selectively varying the capacity of the substituted enabled unit.

Abstract: A bus contention circuit, is employed for each unit of a system capable of seizing use of a bus, wherein the units are arranged in a priority order. Priority resolution is accomplished by registering a request to seize use of the bus from any unit where either (1) no other requests are so registered or (2) the requesting unit is of lower priority than a unit whose request is already registered. When the bus becomes available for use, use is allocated to the unit with highest priority whose request is already registered.

Abstract: Circuit arrangements are disclosed for receiving an applied analog type voltage signal, and in response to the applied signal generating an output pulse string whose frequency characteristic is proportional to the square of the applied signal. In one embodiment a circuit means for creating a jittering effect is provided so as to smear or smooth abrupt discontinuities in the output pulse string. The smearing of the output pulse string improves the accuracy of its frequency characteristic.

Abstract: Input-output buffers interface a data terminal, such as a digital signal processor adapted to perform complex arithmetic functions on vectors of data words, with a storage controller. The input buffer interfaces the storage controller with the data terminal and generates control signals indicating when it is in condition to receive a vector of data words from the storage controller, whereon the storage controller transfers a vector of data to the input buffer; and, further, generates signals indicating when it contains a complete vector of data at which time the input buffer will transfer the vector of data contained therein to the data terminal.

Abstract: The control system for periodically synchronizing in a sequential order the operation of a plurality of control elements of a printing machine comprises a control shift register having an input coupled to a fine timing device for generating synchronizing pulses corresponding to predetermined angular positions of the machine and another input connected to a sheet feeding control device. The outputs of a predetermined number of first stages in the control shift register are connected to a gating nonoperative time compensator, the control inputs of which are connected to the rotary speed detector and the output of which is connected to an assigned operation control element in the machine. A transfer shift register is connected in series with the control shift register or with the output of the dead time compensator.

Abstract: A sidelock avoidance scheme for preventing sidelock in a PSK demodulator's carrier recovery loop contains augmenting sweep control circuitry, including a frequency discriminator and an associated window comparator. The output of the frequency discriminator, which is low pass filtered to remove noise, is applied to the window comparator which compares any differential between the true carrier and the output of a carrier recovery loop to a preset reference threshold representative of a frequency error condition that may approach sidelock. When the output of the frequency discriminator is greater that this preset reference threshold, an augmented frequency control voltage is applied to the voltage control oscillator of the loop to drive the oscillator away from a possible sidelock condition and toward the true carrier. The augmented frequency control voltage may be derived from a frequency sweep generator or from the output of the frequency discriminator, depending upon a selected strapping option.

Abstract: A variable voltage control oscillator can have its output frequency varied over a wide range of frequencies with a high degree of accuracy at each frequency and a rapid tune time is achieved when there is a reference signal source that runs at a constant frequency and is held to a high degree of accuracy and a counter for normalizing the output frequency of the VCO and a coincidence detector which compares the reference frequency to the normalized output frequency and provides an error correcting signal that adjusts the VCO to change the frequency very rapidly without having a frequency overshoot.

Abstract: A controllable LC oscillator has a constant inductance and a constant capacitance. In an oscillator circuit comprising a parallel resonant circuit, voltage limiting components are connected in parallel with the resonant circuit. By way of a controllable impressed current source, the starting point of voltage limitation is controlled and, hence, an alteration of the oscillator frequency is effected. In addition, a dual of the oscillator circuit is provided comprising a series resonant circuit.

Abstract: An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.

Abstract: An oscillator circuit adapted for use as a voltage controlled oscillator in which all of the transistors of the oscillator circuit are operated in non-saturated regions so that the minority carrier accumulation time does not affect the maximum operating frequency of the circuit. First and second current mirror circuits are coupled to opposed outputs of a differential amplifier circuit and are coupled to charge and discharge a capacitor with constant current in response to the states of the differential amplifier circuit. The differential amplifier circuit is provided with a hysteresis characteristic.

Abstract: A report generation control system for operating a text processor to produce output reports containing inter-report summary data from data processing-type files. The system is compatible with text pagination functions and is useable by a text entry/revision operator with no programming skills. The system permits the operator to describe the desired report by keying an example page of the report in the exact desired format and then editing the example page by replacing the required variable file data examples with descriptive instructions and by inserting summary instructions. The system scans the edited example page for instructions, breaks it down into logical components and compiles the components into program routines which will produce the desired output report.

Abstract: Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit.

Abstract: A two-level storage system selectively enables early discard of data from an upper level either immediately or at the end of a predetermined sequence of operation. A copy of data in such upper level is discarded immediately while altered copies of data are discarded at the end of the predetermined sequence of operations. Error conditions inhibit discarding altered data.

Abstract: A frequency regulated crystal oscillator with (1) an oscillating circuit made up of an amplifier, piezoelectric crystal and voltage controls capacitor, and (2) a two-part compensating circuit connected to the terminals of the variable capacitor, each part having thermistors whose resistance varies with temperature to produce complementary signals and which are shunted with electrical resistors.

Abstract: A portable electronic calculator which has incorporated therein a writing instrument. A miniature electronic calculator is built in a rectangular, elongated body. A cover made of metal covers a control panel for the electronic calculator and a display part, and the cover is mounted on the body to be removable therefrom by sliding the cover in the lengthwise direction of the body. The side marginal portions of the cover are bent inwardly for engagement with both side surfaces of the body to reinforce the body when the cover has been mounted thereon.

Abstract: A bit synchronizer for digital data signals capable of tracking phase errors of up to .+-.180.degree. without loss of lock. An input data signal is squared and then applied to a pair of D-type flip-flops. The flip-flops are alternately driven by a clock signal generated by a voltage controlled oscillator in a phase-locked loop. The flip-flops cause the input data to be shifted 0.degree. and 180.degree., respectively, with reference to the clock signal. The flip-flops are cross-coupled to a pair of exclusive-OR gates, in a manner such that as the phase error between the input signal and the clock signal increases or decreases, the pulse width out of one gate varies proportionately while the output of the other gate is a pulse which is always one-half the clock signal period. The phase relationship of the pulses out of the gates switch 180.degree. as the phase error traverses the 0.degree. point.

Abstract: A linearity test signal generator alternately provides a burst of a modulation frequency and no modulation to the modulation input of the frequency modulator oscillator (FMO) under test. A programmable divider is connected to the output of said frequency modulated oscillator to produce a binary output signal which is applied to the automatic phase control circuit. This circuit in turn develops a DC control signal which is applied to the control input of said frequency modulated oscillator to maintain the average oscillator frequency constant. This DC control voltage gives an indication of the shift in the average free running frequency of the oscillator while being modulated, caused by oscillator non-linearity. The voltage is first sampled when the oscillator is unmodulated to produce a reference voltage which is stored and then compared to a sample of the DC control voltage when the oscillator is being modulated.

Abstract: To provide for tuning of an oscillator circuit, a plurality of resistors are selectively connectable in the circuit. To provide for reproducible, accurate oscillation frequency in accordance with switching of a respective resistor in dependence on a digital input signal, electronic switches are respectively connected to the resistors to connect them in circuit in the oscillator to thereby eliminate variable contact resistances of mechanical switches. A digital frequency control signal is generated by placing a movable mask or pattern with openings therein between an array, for example a linear strip of light emitting diodes, and a similar strip of photo transistors, the respective energization of which is determined by openings in the diaphragm. The signals from the photo transistors are stored in a memory, typically a group of flip-flops, for application to the electronic switches controlling connection of the respective resistors in the oscillator circuit.

Abstract: A data buffer circuit is disclosed for receiving from a serial-to-parallel ata conversion interface circuit a plurality of sixteen-bit parallel data words, for storing therein for a predetermined time period each of the parallel data words, and for transferring to a computer, so as to allow for processing by the computer, each of the parallel data words.

Abstract: A novel negative resistance oscillator is disclosed for partial integration. The oscillator has a tank circuit and a load, which are non-integrated, and active circuitry, which is integrated. The active circuit consists of a current "source" and two current "sinks", arranged to provide a negative resistance. The oscillator, which is designed to drive an erase head in a tape recorder, as a part of a tape recorder integrated circuit, requires only a single additional pin, has a controlled peak current range, a large dc voltage swing for a given dc supply potential, and an efficient dc to ac current conversion ratio.