Patents Examined by Timor Karimy
  • Patent number: 11462481
    Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 4, 2022
    Assignee: Kore Semiconductor Co., Ltd.
    Inventors: Ying-Chieh Pan, Hsiang-Hua Lu, Ching-Yu Ni
  • Patent number: 11456279
    Abstract: A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Qi Deng
  • Patent number: 11450645
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11450581
    Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
  • Patent number: 11444012
    Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Chang-Yen Ko, Chih-Chien Ho
  • Patent number: 11444028
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 11444034
    Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 11430767
    Abstract: A semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; vertical interconnectors, each having first ends that are connected to the plurality of semiconductor chips, respectively, and extending in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; landing pads formed over one surface of the molding layer to be in contact with the second ends of the vertical interconnectors, respectively, wherein the landing pads are conductive and overlap the first ends of the vertical interconnectors, respectively; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventors: Chaesung Lee, Jonghoon Kim, Bokkyu Choi, Kijun Sung
  • Patent number: 11424236
    Abstract: In certain embodiments, a method for designing a semiconductor device includes generating a two-dimensional design for fabricating chiplets on a semiconductor substrate. The chiplets are component levels for a multi-chip integrated circuit. The two-dimensional design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The second chiplet is adjacent to the first chiplet on the semiconductor substrate. The second layout is a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet. The first surface of the first chiplet and the first surface of the second chiplet are both either top surfaces or bottom surfaces. The method further includes generating a photomask according to the design.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 23, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Robert Clark
  • Patent number: 11424220
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Yang Yu, Kuan-Lin Ho, Chin-Liang Chen, Yu-Min Liang
  • Patent number: 11417602
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Li Chun Te
  • Patent number: 11410984
    Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 9, 2022
    Assignee: Silicon Genesis Corporation
    Inventors: Michael I. Current, Theodore E. Fong
  • Patent number: 11411748
    Abstract: A method for producing a PUF-film includes printing a layer of dielectric material on a film substrate, such that a variable thickness of the layer is obtained by the printing. The method includes arranging a structured electrode layer on the dielectric material such that the structured electrode layer is influenced with respect to an electric measurement value due to the variable thickness.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 9, 2022
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Martin Koenig
  • Patent number: 11410957
    Abstract: At least some embodiments of the present disclosure relate to a method for manufacturing a bonding structure. The method includes: providing a substrate with a seed layer; forming a conductive pattern on the seed layer; forming a dielectric layer on the substrate and the conductive pattern; and removing a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao Hsuan Chuang, Huang-Hsien Chang
  • Patent number: 11411147
    Abstract: A wavelength converting layer is partially diced to generate a first and second wavelength converting layer segment and to allow partial isolation between the first segment and the second segment such that the wavelength converting layer segments are connected by a connecting wavelength converting layer. The first and second wavelength converting layer segments are attached to a first and second light emitting device, respectively to create a first and second pixel. The connecting wavelength converting layer segment is removed to allow complete isolation between the first pixel and the second pixel. An optical isolation material is applied to exposed surfaces of the first and second pixel and a sacrificial portion of the wavelength converting layer segments and optical isolation material attached to the sacrificial portion is removed from a surface facing away from the first light emitting device, to expose a emitting surface of the first wavelength converting layer segment.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 9, 2022
    Assignee: Lumileds LLC
    Inventors: Kentaro Shimizu, Hisashi Masui, Yu-Chen Shen, Danielle Russell Chamberlin, Peter Josef Schmidt
  • Patent number: 11404475
    Abstract: Connection with a wiring structure can be reliably achieved, whereby a semiconductor sensor device and a semiconductor sensor device manufacturing method with increased reliability are provided. A semiconductor sensor device in which a multiple of signal lines and a sensor detection portion are disposed includes a conductive film, disposed on a substrate, that configures the signal lines and whose upper face is exposed by an aperture portion of a width smaller than a width of the signal lines, a conductive member formed on the conductive film and electrically connected to the conductive film via the aperture portion, and a wiring structure, formed on an upper face of the conductive member, of an air bridge structure that connects the signal lines or the signal lines and the sensor detection portion, wherein an upper surface of the conductive member is in contact with the wiring structure, and a side face is exposed.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 2, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiromoto Inoue, Shinichi Hosomi, Yoshitatsu Kawama, Takaki Sugino
  • Patent number: 11404349
    Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Ravindranath V. Mahajan, Robert L. Sankman, James C. Matayabas, Jr., Ken P. Hackenberg, Nayandeep K. Mahanta, David D. Olmoz
  • Patent number: 11393735
    Abstract: A semiconductor device is disclosed having reinforced supports at corners of the device. The semiconductor device may include solder balls on a lower surface of the device for soldering the device onto a printed circuit board. In one example, the solder balls at the corners of the semiconductor device may be replaced by support billets having more mass and more contact area between the semiconductor device and the PCB. In a further example, screws may be provided at the corners of the device (instead of the corner solder balls or in addition to the corner solder balls). These screws may be placed through the corners of the semiconductor device and into the printed circuit board.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yangming Liu, Ning Ye, Chin-Tien Chiu
  • Patent number: 11393806
    Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Analog Devices, Inc.
    Inventors: James G. Fiorenza, Puneet Srivastava, Daniel Piedra
  • Patent number: 11380601
    Abstract: A semiconductor chip is mounted on a substrate in a face-down manner. A metal film is arranged on a back surface of the semiconductor chip facing an opposite side from the substrate away from an edge of the back surface. A sealing resin layer seals the semiconductor chip with a part of the metal film being exposed from the sealing resin layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Yuichi Sano, Toshihiro Tada