Patents Examined by Timor Karimy
  • Patent number: 12148736
    Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: November 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, Seng Kim Ye, Chin Hui Chong
  • Patent number: 12148858
    Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs. An edge of the top spacer is aligned with an edge of the light emitting layer, and an edge of the bottom spacer is aligned with the edge of the light emitting layer.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 19, 2024
    Assignee: JADE BIRD DISPLAY (SHANGHAI) LIMITED
    Inventors: Qiming Li, Yuankun Zhu, Anle Fang, Deshuai Liu
  • Patent number: 12144267
    Abstract: According to one embodiment, a selector device includes a first electrode, a second electrode, and a selector layer disposed between the first electrode and the second electrode. At least one of the first electrode or the second electrode includes a stacked film. The stacked film includes a first layer including a first material with a first Debye temperature, and a second layer in contact with the first layer and including a second material with a second Debye temperature lower than the first Debye temperature. A ratio of the first Debye temperature to the second Debye temperature is equal to or greater than 5.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 12, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Jieqiong Zhang, Masatoshi Yoshikawa, Tadaomi Daibou
  • Patent number: 12142696
    Abstract: A thin film transistor is provided. The thin film transistor includes abase substrate; a gate electrode on the base substrate; an active layer on the base substrate, the active layer including a polycrystalline silicon part including a polycrystalline silicon material and an amorphous silicon part including an amorphous silicon material; a gate insulating layer insulating the gate electrode from the active layer; a source electrode and a drain electrode on the base substrate; and an etch stop layer on a side of the polycrystalline silicon part away from the base substrate. An orthographic projection of the etch stop layer on the base substrate covers an orthographic projection of the polycrystalline silicon part on the base substrate, and an orthographic projection of at least a portion of the amorphous silicon part on the base substrate.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 12, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Feng Guan, Yichi Zhang, Yang Lv
  • Patent number: 12136607
    Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: November 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa, Chang H. Siau
  • Patent number: 12127351
    Abstract: A method and assembly for board to board connection of active devices are described herein. The assembly comprises first and second superposed active devices, a first interfacing member electrically coupled to the first active device, and a flexible printed wiring board having a first end and a second end, the first end electrically coupled to the first interfacing member.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 22, 2024
    Assignee: Smiths Interconnect Canada Inc.
    Inventor: David R. Rolston
  • Patent number: 12101973
    Abstract: A display substrate and a display device are provided. The display substrate includes a first power signal line and a pixel defining layer. The first power signal line includes first power signal sub-lines extending along a first direction and second power signal sub-lines extending along a second direction. The pixel defining layer includes a plurality of openings to define effective light-emitting regions of a plurality of sub-pixels, the plurality of sub-pixels include a sub-pixel pair including two sub-pixels arranged along the second direction, and the sub-pixel pair includes two effective light-emitting sub-regions with an interval therebetween. In a plan view, the first power signal sub-line passes through the interval between the two effective light-emitting sub-regions, at least one second power signal sub-line includes a fracture, and the two effective light-emitting sub-regions are located at the fracture.
    Type: Grant
    Filed: April 26, 2020
    Date of Patent: September 24, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Biao Liu, Mengmeng Du, Xiangdan Dong, Hongwei Ma
  • Patent number: 12101964
    Abstract: A display apparatus includes a substrate including an emission area and a non-emission area surrounding the emission area, a planarization layer formed on the substrate, a light emitting device disposed on the planarization layer, and including an anode electrode, and a separation layer disposed to be spaced apart from the anode electrode on the planarization layer, wherein the planarization layer is formed to overlap at least a portion of the non-emission area and includes a trench portion formed by removing at least a portion of the planarization layer, the trench portion at least partially overlaps an end of each of the anode electrode and the separation layer in the non-emission area, the light emitting device further including a light emitting layer and a cathode electrode sequentially formed on the anode electrode, and the light emitting layer and the cathode electrode are discontinuously formed in the trench portion.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: September 24, 2024
    Assignee: LG Display Co., Ltd.
    Inventor: Howon Choi
  • Patent number: 12094890
    Abstract: The present application provides a sensor module, a method for manufacturing the sensor module, and a display panel. The sensor module is integrated by a light-sensitive PN junction and a bottom-gate thin film transistor, a limitation of an integration of top-gate thin film transistor photosensitive sensor is prevented, and a problem of increased thickness and development cost in an integration of a photosensitive sensor on a bottom surface and the display panel is solved.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 17, 2024
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jinming Li
  • Patent number: 12087737
    Abstract: A method of forming a package comprises forming a stack of chip layers. Each chip layer has a front side facing away from the carrier substrate. A first chip layer includes a plurality of first chips having first chip contacts on the front side of the first chip layer and chip couplers having through vias. A second chip layer includes a plurality of second chip having second chip contacts on the front side of the second chip layer and coupled to respective ones of at least a first subset of the through vias. The method further comprises forming a redistribution layer on the front side of the first chip layer and dividing the stack of chip layers and the redistribution layer to form a plurality of chip packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: September 10, 2024
    Assignee: Yibu Semiconductor Co., Ltd.
    Inventor: Weiping Li
  • Patent number: 12087877
    Abstract: A light-emitting element includes a first n-type contact layer, a light-emitting layer that is located on the first n-type contact layer and emits light at a wavelength of not less than 210 nm and not more than 365 nm, a p-type layer that includes AlxGayIn1-x-yN (0?x+y?1, 0?x, y?1) and is located above the light-emitting layer, a second n-type contact layer that includes AlxGayIn1-x-yN (0?x+y?1, 0?x, y?1), is located on the p-type layer and forms a tunnel junction with the p-type layer, an n-electrode connected to the first n-type contact layer, and a p-electrode connected to the second n-type contact layer. Band gaps of the p-type layer and the second n-type contact layer are larger than a band gap of the light-emitting layer.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: September 10, 2024
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Kengo Nagata
  • Patent number: 12088065
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: September 10, 2024
    Assignee: KYOCERA SLD Laser, Inc.
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Patent number: 12080795
    Abstract: A semiconductor device includes a base substrate, a first electrode plate on the base substrate, a first power rail on the first electrode plate, the first power rail extending in a first horizontal direction and overlapping the first electrode plate in a vertical direction, a second power rail on the first electrode plate, the second power rail extending in the first horizontal direction and overlapping the first electrode plate in the vertical direction, and the second power rail being spaced apart from the first power rail in a second horizontal direction different from the first horizontal direction, a first power rail contact electrically connecting the first electrode plate and the first power rail, an insulating layer on the base substrate to surround the first electrode plate, the first power rail, and the second power rail, and a gate electrode extending in the second horizontal direction on the insulating layer.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: September 3, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung Min Kim
  • Patent number: 12075687
    Abstract: A mask includes: a body portion including a cell area, and a peripheral area surrounding the cell area, the body portion having a plurality of cell openings defined therein; and a plurality of mark patterns at the peripheral area. The cell area includes: a first area; and a second area adjacent to the first area, and the plurality of cell openings includes: first cell openings defined at the first area, and spaced from each other; and second cell openings defined at the second area, and spaced from each other. Each of the mark patterns includes at least one recess portion, and has a point-symmetrical shape with respect to a corresponding symmetry point.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 27, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangshin Lee, Sanghoon Kim, Seil Kim, Hong-Kyun Ahn, Jongsung Park, Seungjin Lee
  • Patent number: 12074139
    Abstract: A support piece formation laminate film according to the present disclosure includes a base material film, a pressure-sensitive adhesive layer, and a support piece formation film, in this order, in which the support piece formation film has a multi-layer structure including at least a metal layer. The support piece formation laminate film is applied to a manufacturing process of a semiconductor device having a dolmen structure including a substrate, a first chip disposed on the substrate, a plurality of support pieces disposed around the first chip, on the substrate, and a second chip disposed to be supported by the plurality of support pieces and to cover the first chip.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 27, 2024
    Inventors: Tatsuya Yahata, Kohei Taniguchi, Shintaro Hashimoto, Yoshinobu Ozaki, Kei Itagaki
  • Patent number: 12068191
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Patent number: 12062613
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Chun-Te Li
  • Patent number: 12063827
    Abstract: A display substrate and a display device are provided. The display substrate includes a first power signal line and a pixel defining layer. The first power signal line includes first power signal sub-lines extending along a first direction and second power signal sub-lines extending along a second direction. The pixel defining layer includes a plurality of openings to define effective light-emitting regions of a plurality of sub-pixels, the plurality of sub-pixels include a sub-pixel pair including two sub-pixels arranged along the second direction, and the sub-pixel pair includes two effective light-emitting sub-regions with an interval therebetween. In a plan view, the first power signal sub-line passes through the interval between the two effective light-emitting sub-regions, at least one second power signal sub-line includes a fracture, and the two effective light-emitting sub-regions are located at the fracture.
    Type: Grant
    Filed: April 26, 2020
    Date of Patent: August 13, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Biao Liu, Mengmeng Du, Xiangdan Dong, Hongwei Ma
  • Patent number: 12041821
    Abstract: According to one embodiment, a display panel includes a substrate, a first insulating layer, and a plurality of pixels including sub-pixels of a plurality of colors, respectively. Each of the sub-pixels includes a drive transistor, a pixel electrode supplied with a signal having a current value controlled from the drive transistor, and a light emitting element mounted on the pixel electrode. Each of the pixels includes a mounting electrode located to be spaced apart from the pixel electrode. The mounting electrode is in an electrically floating state in a first pixel of the plurality of pixels.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: July 16, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Yasuhiro Kanaya, Masanobu Ikeda
  • Patent number: 12033946
    Abstract: In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 9, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ji Young Chung, Seung Chul Jang, Ron Huemoeller