Patents Examined by Timor Karimy
  • Patent number: 10998378
    Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Jean-Jacques Fagot
  • Patent number: 10985118
    Abstract: A method and a high-frequency module that includes (a) a high frequency die that includes multiple die pads, (b) a substrate that comprises a first buildup layer, a second buildup layer and a core that is positioned between the first buildup layer and a second buildup layer, (c) a heat sink and coupling module that comprises a heat sink and multiple first conductors that pass through the heat sink and extend outside the heat sink; (d) a line card that comprises multiple line card pads that are coupled to external ends of the multiple first conductors; (e) coupling elements that are coupled to internal end of the multiple first conductors; and (f) multiple second conductors that pass through the substrate without reaching a majority of a depth of the core, and couple the multiple die pads to the coupling elements. The high frequency it not lower than fifty gigabits per second.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 20, 2021
    Assignees: XSIGHT LABS LTD., DustPhotonics
    Inventors: Guy Koren, Ben Rubovitch
  • Patent number: 10978607
    Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 13, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere
  • Patent number: 10978555
    Abstract: A method of forming a semiconductor structure includes the following steps. A dielectric stack is formed on a bottom metal. A first mask layer is formed on the dielectric stack. The first mask layer has a plurality of first through holes, and a portion of the first through holes is in a central portion of the first mask layer. A second mask layer is formed on the first mask layer and in the first through holes. The second mask layer is patterned to form an opening between a central portion of the second mask layer covers the portion of the first through holes and is surrounded by the peripheral portion. The dielectric stack is etched below the first through holes the second through hole. A conductive layer is formed in the second through hole and on a top surface of the dielectric stack.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Piao Chang
  • Patent number: 10971663
    Abstract: To improve light emission efficiency and suppress color unevenness on a light emitting surface. Provided is a semiconductor light emitting device including a light emitting element, a wavelength conversion layer for converting light emitted from the light emitting element to light having a predetermined wavelength, a light reflection member covering at least the side surfaces of the wavelength conversion layer, and a thin film provided on the outermost surface from which the light wavelength-converted by the wavelength conversion layer exits, having a property for shedding the uncured light reflection member, and having a coarse surface.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 6, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Kaori Tachibana
  • Patent number: 10950605
    Abstract: A semiconductor device includes a first transistor. The first transistor includes a first terminal, a first contact, a second terminal, and a second contact. The first contact is electrically connected to the first terminal, and the shape of the first contact is circular. The second contact is electrically connected to the second terminal and a ground terminal, and the shape of the second contact is rectangular.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10943974
    Abstract: A channel stopper region extending from a first main surface into a component layer of a first conductivity type is formed in an edge region of a component region, the edge region being adjacent to a sawing track region. Afterward, a doped region extending from the first main surface into the component layer is formed in the component region. The channel stopper region is formed by a photolithographic method that is carried out before a first photolithographic method for introducing dopants into a section of the component region outside the channel stopper region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Elmar Falck, Franz-Josef Niedernostheide, Hans-Joachim Schulze
  • Patent number: 10943979
    Abstract: The disclosure relates to a semiconductor device having a SiC semiconductor body. The SiC semiconductor body includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region is electrically contacted at a first surface of the SiC semiconductor body and forms a pn junction with the second semiconductor region. The first semiconductor region and the second semiconductor region are arranged one above the other in a vertical direction perpendicular to the first surface. The first semiconductor region has a first dopant species and a second dopant species.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Rainer Stegner, Hans-Joachim Schulze
  • Patent number: 10937757
    Abstract: Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: March 2, 2021
    Assignee: SEMIgear, Inc.
    Inventors: Jian Zhang, Joshua Pinnolis, Shijian Luo
  • Patent number: 10923396
    Abstract: Electronic devices and methods to form electronic devices having a self-aligned via are described. An adhesion enhancement layer is utilized to promote adhesion between the conductive material and the sidewalls of the at least one via opening. The self-aligned vias decrease via resistance and reduce the potential to short to the wrong metal line.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Mihaela Balseanu
  • Patent number: 10923566
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes a substrate and an annular nanowire disposed over the substrate.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Yung-Ta Li, Meng-Ku Chen
  • Patent number: 10916443
    Abstract: A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Yung-Hsu Wu
  • Patent number: 10916684
    Abstract: A light emitting device including a plurality light emitting diodes configured to produce a primary light; a wavelength conversion means configured to at least partially convert the primary light into secondary light having peak emission wavelength ranges between 450 nm and 520 nm, between 500 nm and 570 nm, and between 570 nm and 680 nm; and a molded part to enclose the light emitting diodes and the wavelength conversion means.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 9, 2021
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Chung-Hoon Lee, Gundula Roth, Walter Tews
  • Patent number: 10903625
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 26, 2021
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Patent number: 10903363
    Abstract: A ferroelectric semiconductor device of the present disclosure includes a substrate, a ferroelectric layer disposed on the substrate, an electric field control layer that is disposed on the ferroelectric layer and has a predetermined internal electric field formed without the application of an external electric power to alter the magnitude of a coercive electric field of the ferroelectric layer, and a gate electrode layer disposed on the electric field control layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Yong Soo Choi
  • Patent number: 10896891
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of first pad electrodes provided above the semiconductor substrate; a plurality of first wires electrically connected to the plurality of first pad electrodes respectively; a first electrode commonly connected to the plurality of first wires; a second pad electrode provided above the semiconductor substrate; and a first resistance portion and a first protective element that are connected in series between the first electrode and the second pad electrode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yu Suzuki, Shoko Kikuchi, Merii Inaba, Jun Murakami, Takashi Shigeoka, Hiroshi Inagaki, Takashi Okuhata
  • Patent number: 10892218
    Abstract: A first power supply terminal P is provided with an internal wiring connection portion 31A, an upright portion 31B which is joined to the internal wiring connection portion 31A, an inclined portion 31C which is joined to the upright portion 31B and an external wiring connection portion 31D which is joined to the inclined portion 31C. A second power supply terminal N is provided with an internal wiring connection portion 32A, an upright portion 32B which is joined to the internal wiring connection portion 32A, an inclined portion 32C which is joined to the upright portion 32B and an external wiring connection portion 32D which is joined to the inclined portion 32C. The upright portion 31B of the first power supply terminal P and the upright portion 32B of the second power supply terminal N are arranged so as to face each other, with a predetermined interval kept therebetween.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: January 12, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Yoshihisa Tsukamoto, Masashi Hayashiguchi, Soichiro Takahashi
  • Patent number: 10892254
    Abstract: Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).
    Type: Grant
    Filed: May 11, 2019
    Date of Patent: January 12, 2021
    Inventors: Zhanming Li, Guanhou Luo, Yue Fu, Wai Tung Ng, Yan-Fei Liu
  • Patent number: 10886161
    Abstract: A method for manufacturing a semiconductor device according to embodiments may include forming a sacrificial layer on a first substrate including first dopant atoms and second dopant atoms, and forming a germanium (Ge) layer on the sacrificial layer. Here, the germanium (Ge) layer may include the first dopant atoms diffused from the first substrate by growth temperature in the forming step. Additionally, the method for manufacturing a semiconductor device may further include annealing after growth of the germanium (Ge) layer so that the germanium (Ge) layer may include second dopant atoms.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: January 5, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyung-jun Kim, Sanghyeon Kim, Hansung Kim, Seong Kwang Kim, Hyeong Rak Lim
  • Patent number: 10886156
    Abstract: A receiving means for receiving and mounting of wafers, comprised of a mounting surface, mounting means for mounting a wafer onto the mounting surface and compensation means for active, locally controllable, compensation of local and/or global distortions of the wafer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: January 5, 2021
    Assignee: EV Group E. Thallner GmbH
    Inventors: Markus Wimplinger, Thomas Wagenleitner, Alexander Filbert