Abstract: A semiconductor package includes a chip stack comprising semiconductor chips vertically stacked on a substrate in a first direction perpendicular to a top surface of the substrate, pillars between the substrate and the chip stack, an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips, a first lower protective layer between the adhesive layer and the pillars, a second lower protective layer between the first lower protective layer and the adhesive layer, and a mold layer covering the chip stack and filling a space between the pillars. A thickness of the second lower protective layer in the first direction is greater than a thickness of the adhesive layer in the first direction.

Abstract: A component carrier which includes a laminated stack having at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, and a component having at least one electrically conductive connection structure and embedded in the stack, wherein the at least one electrically conductive connection structure of the component is exposed with respect to the stack so that a free exposed end of the at least one electrically conductive connection structure of the component is flush with or extends beyond an exterior main surface of the stack.

Abstract: A nitride-based semiconductor device including a first and a second nitride-based semiconductor layers, a source electrode and a drain electrode, and a gate structure. The gate structure includes at least one conductive layer and two or more doped nitride-based semiconductor layers. The at least one conductive layer includes metal, and is in contact with the second nitride-based semiconductor layer to form a metal-semiconductor junction therebetween. The two or more doped nitride-based semiconductor layers are in contact with the second nitride-based semiconductor layer and abut against the conductive layer, so as to form contact interfaces abutting against the metal-semiconductor junction with the second nitride-based semiconductor.

Abstract: A display panel, a display apparatus and a preparation method of a display panel. The display panel includes a substrate, a display region and a non-display region. The non-display region includes a hole region and an isolation region adjoining the display region and the hole region. The isolation region includes at least one second isolation structure at least partially surrounding the hole region. The second isolation structure includes a supporting portion and a partitioning portion located on the supporting portion. An orthographic projection of the partitioning portion on the substrate covers an orthographic projection of the supporting portion on the substrate, and a maximum width of the supporting portion is smaller than a width of the partitioning portion. A tensile stress layer configured to apply a tensile stress to the partitioning portion is disposed on the partitioning portion.

Abstract: A micro-LED structure includes a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer extends along a horizontal level away from a top edge of the first type conductive layer and a bottom edge of the second type conductive layer, such that an edge of the light emitting layer does not contact the top edge of the first type conductive layer and the bottom edge of the second type conductive layer. A profile of the first type conductive layer perpendicularly projected on a bottom surface of the second type conductive layer is surrounded by the bottom edge of the second type conductive layer.

Abstract: A memory device includes a first chip and a second chip. The first chip includes a first storage array and a second storage array. The first storage array includes at least one first storage block. The first storage block includes a plurality of first word lines extending in a first direction and a plurality of first bit lines extending in a second direction. The second storage array includes at least one second storage block. By constructing a first global bit line sub-decoder block in a first overhead projection area formed by the first storage block and constructing a second global bit line sub-decoder block in a second overhead projection area formed by the second storage block, an occupied area of the first chip and the second chip after stacking can be reduced, which reduces an occupied area of the memory device and is beneficial for minimizing the memory device.

Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs. An edge of the top spacer is aligned with an edge of the light emitting layer, and an edge of the bottom spacer is aligned with the edge of the light emitting layer.

Abstract: According to one embodiment, a selector device includes a first electrode, a second electrode, and a selector layer disposed between the first electrode and the second electrode. At least one of the first electrode or the second electrode includes a stacked film. The stacked film includes a first layer including a first material with a first Debye temperature, and a second layer in contact with the first layer and including a second material with a second Debye temperature lower than the first Debye temperature. A ratio of the first Debye temperature to the second Debye temperature is equal to or greater than 5.

Abstract: A thin film transistor is provided. The thin film transistor includes abase substrate; a gate electrode on the base substrate; an active layer on the base substrate, the active layer including a polycrystalline silicon part including a polycrystalline silicon material and an amorphous silicon part including an amorphous silicon material; a gate insulating layer insulating the gate electrode from the active layer; a source electrode and a drain electrode on the base substrate; and an etch stop layer on a side of the polycrystalline silicon part away from the base substrate. An orthographic projection of the etch stop layer on the base substrate covers an orthographic projection of the polycrystalline silicon part on the base substrate, and an orthographic projection of at least a portion of the amorphous silicon part on the base substrate.

Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Abstract: A method and assembly for board to board connection of active devices are described herein. The assembly comprises first and second superposed active devices, a first interfacing member electrically coupled to the first active device, and a flexible printed wiring board having a first end and a second end, the first end electrically coupled to the first interfacing member.

Abstract: A display substrate and a display device are provided. The display substrate includes a first power signal line and a pixel defining layer. The first power signal line includes first power signal sub-lines extending along a first direction and second power signal sub-lines extending along a second direction. The pixel defining layer includes a plurality of openings to define effective light-emitting regions of a plurality of sub-pixels, the plurality of sub-pixels include a sub-pixel pair including two sub-pixels arranged along the second direction, and the sub-pixel pair includes two effective light-emitting sub-regions with an interval therebetween. In a plan view, the first power signal sub-line passes through the interval between the two effective light-emitting sub-regions, at least one second power signal sub-line includes a fracture, and the two effective light-emitting sub-regions are located at the fracture.

Abstract: A display apparatus includes a substrate including an emission area and a non-emission area surrounding the emission area, a planarization layer formed on the substrate, a light emitting device disposed on the planarization layer, and including an anode electrode, and a separation layer disposed to be spaced apart from the anode electrode on the planarization layer, wherein the planarization layer is formed to overlap at least a portion of the non-emission area and includes a trench portion formed by removing at least a portion of the planarization layer, the trench portion at least partially overlaps an end of each of the anode electrode and the separation layer in the non-emission area, the light emitting device further including a light emitting layer and a cathode electrode sequentially formed on the anode electrode, and the light emitting layer and the cathode electrode are discontinuously formed in the trench portion.

Abstract: The present application provides a sensor module, a method for manufacturing the sensor module, and a display panel. The sensor module is integrated by a light-sensitive PN junction and a bottom-gate thin film transistor, a limitation of an integration of top-gate thin film transistor photosensitive sensor is prevented, and a problem of increased thickness and development cost in an integration of a photosensitive sensor on a bottom surface and the display panel is solved.

Abstract: A method of forming a package comprises forming a stack of chip layers. Each chip layer has a front side facing away from the carrier substrate. A first chip layer includes a plurality of first chips having first chip contacts on the front side of the first chip layer and chip couplers having through vias. A second chip layer includes a plurality of second chip having second chip contacts on the front side of the second chip layer and coupled to respective ones of at least a first subset of the through vias. The method further comprises forming a redistribution layer on the front side of the first chip layer and dividing the stack of chip layers and the redistribution layer to form a plurality of chip packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.

Abstract: A light-emitting element includes a first n-type contact layer, a light-emitting layer that is located on the first n-type contact layer and emits light at a wavelength of not less than 210 nm and not more than 365 nm, a p-type layer that includes AlxGayIn1-x-yN (0?x+y?1, 0?x, y?1) and is located above the light-emitting layer, a second n-type contact layer that includes AlxGayIn1-x-yN (0?x+y?1, 0?x, y?1), is located on the p-type layer and forms a tunnel junction with the p-type layer, an n-electrode connected to the first n-type contact layer, and a p-electrode connected to the second n-type contact layer. Band gaps of the p-type layer and the second n-type contact layer are larger than a band gap of the light-emitting layer.

Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.

Abstract: A semiconductor device includes a base substrate, a first electrode plate on the base substrate, a first power rail on the first electrode plate, the first power rail extending in a first horizontal direction and overlapping the first electrode plate in a vertical direction, a second power rail on the first electrode plate, the second power rail extending in the first horizontal direction and overlapping the first electrode plate in the vertical direction, and the second power rail being spaced apart from the first power rail in a second horizontal direction different from the first horizontal direction, a first power rail contact electrically connecting the first electrode plate and the first power rail, an insulating layer on the base substrate to surround the first electrode plate, the first power rail, and the second power rail, and a gate electrode extending in the second horizontal direction on the insulating layer.

Abstract: A mask includes: a body portion including a cell area, and a peripheral area surrounding the cell area, the body portion having a plurality of cell openings defined therein; and a plurality of mark patterns at the peripheral area. The cell area includes: a first area; and a second area adjacent to the first area, and the plurality of cell openings includes: first cell openings defined at the first area, and spaced from each other; and second cell openings defined at the second area, and spaced from each other. Each of the mark patterns includes at least one recess portion, and has a point-symmetrical shape with respect to a corresponding symmetry point.