Patents Examined by Timothy M. Bonura
  • Patent number: 7302617
    Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for managing and predicting risk for computer-based systems. Information about a computer-based system is asynchronously received. A risk level at which the computer-based system operates is calculated based on the received information.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: November 27, 2007
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael J. Wookey
  • Patent number: 7240239
    Abstract: The present invention provides an input and output device for computer system storage that can prevent a computer system being fatally damaged by a computer virus, and also provides a software execution method that by using the input and output device, enables trial software, trial data and mail data to be safely tried. For this, a virtual computer system is used that runs on a computer system. Writes to a hard disk in the virtual computer system are made via a disk cache, and whether or not data is transferred from the disk cache to the hard disk is controlled. Application program snapshot data created by the computer system is recorded on a recording medium that is substantially read-only or transmitted to a different computer system. The snapshot data from the recording medium is read or received by the different computer system and a processing by the application program is resumed in the state in which data transfer from the disk cache to the first storage has stopped.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: July 3, 2007
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Kuniyasu Suzaki
  • Patent number: 7216251
    Abstract: An initial setup method (100) stores recovery tools (400) and a further setup script (402) on a computer (1000) which has an operating system (302) that need not have any recovery capabilities. At the user site, a further setup method (700, 800) reserves (706) a container space (500) in the file system space (304), creates (716) an image (1008) of the main partition (300), and stores (720) the image in the container. If the partition is corrupted later, the computer can still be booted using virtual boot tools (602), the image can be retrieved (914) from the container even though the partition around it was lost, and the image can then be deployed onto disk (200) over the corrupted partition, thereby restoring a working partition to the computer. This can be done without secondary media such as a recovery CD or floppy, and without a network connection.
    Type: Grant
    Filed: June 1, 2003
    Date of Patent: May 8, 2007
    Assignee: Powerquest Corporation
    Inventors: Jared R. Gaunt, Val A. Arbon
  • Patent number: 7213171
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Patent number: 7206971
    Abstract: A plurality of selectable memory devices is available for booting a computer processor. The devices may be selected prior to booting, or may be changed upon recognition that the booting process is not proceeding properly. In another use, one device may be reprogrammed with an updated version while keeping the older version present. Once the updated version is functioning properly, the older version may be overwritten so that two known working copies are available.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Jeremy R. Zeller, David E. Hoyer
  • Patent number: 7197665
    Abstract: A backup apparatus and method suitable for protecting the data volume in a computer system function by acquiring a base state snapshot and a sequential series of data volume snapshots, the apparatus concurrently generating succedent and precedent lists of snapshot differences which are used to create succedent and precedent backups respectively. The data volume is restored by overwriting the base state data with data blocks identified in one or more succedent backups. File recovery is accomplished by overwriting data from a current snapshot with one or more precedent backups.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: March 27, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andrew C. Goldstein, David W. Thiel, Richard F. Wrenn
  • Patent number: 7178056
    Abstract: Application software on a fault tolerant system having an active engine and a standby engine is upgraded. As part of the upgrade, the system determines if the active engine and the standby engine are executing different versions of the application software. The system sends a description of work units from the active engine to the standby engine and sends database activities from the active engine to the standby engine.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventor: Vedvyas Shanbhogue
  • Patent number: 7159152
    Abstract: A system and a method are distinguished by the fact that, if it is determined that the system is not operating properly, a control device is stopped and it is ensured that the control device, when operation is continued, begins with the execution of the operation whose faulty execution may be the cause for the fault registered, or which was being executed when the fault was registered. This makes it possible, with little effort and without noticeable disruption to the operation of the system, to determine whether improper operation of the system is of only a temporary nature or of a permanent nature, and for the system or parts of the same to be deactivated or reset only when the fault that has occurred is not a temporary fault.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: January 2, 2007
    Assignee: Infineon Technologies AG
    Inventor: Wihard Christophorus Von Wendorff
  • Patent number: 7152179
    Abstract: Redundant gateway methods, apparatus and systems use more than one gateway device in a gateway device group for communications directed outside of a LAN. Failover services are thus provided in the event that an active router or other gateway device fails. A failover monitoring unit includes a memory and a processor coupled to the memory. The monitoring unit also includes gateway ports connected to the processor. Each gateway port is configured to connect a gateway device to the monitoring unit. The monitoring unit is configured to collect and store redundancy group data pertaining to a redundancy group comprising a plurality of gateway devices connected to the monitoring unit. The redundancy group includes an active gateway device and one or more standby gateway devices. The monitoring unit monitors the gateway ports to detect failure of an active gateway device. When a failure is detected, the monitoring unit notifies each redundancy group standby gateway device of the active gateway device failure.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: December 19, 2006
    Assignee: Cisco Technology, Inc.
    Inventor: Graham Critchfield
  • Patent number: 7149934
    Abstract: As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: December 12, 2006
    Assignee: Contour Semiconductor, Inc.
    Inventor: Daniel Robert Shepard
  • Patent number: 7139927
    Abstract: A journaling method is provided for supporting a recovery when a system is abnormally terminated in a shared disk environment. When a system call operation to take part in a journaling is generated, in order to guarantee a recovery, a transaction is started and new transaction region is assigned. Then, a system is initialized and a transaction type is set up. Lock information on modified data is acquired and added to the transaction so that a transaction manages lock information. A reflection to a disk during a modification of metadata is prevented. Modified metadata added to the transaction and modified information on principal general data are recorded. Then, lock information connected to the transaction is released.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: November 21, 2006
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Choon Seo Park, Gyoung Bae Kim, Bum Joo Shin, Yong-Ju Lee, Seon-Yeong Park
  • Patent number: 7139930
    Abstract: A failover method and system is provided for a computer system having at least three nodes operating as a cluster. One method includes the steps of detecting failure of one node, determining the weight of at least two surviving nodes, and assigning a failover node based on the determined weights of the surviving nodes. Another method includes the steps detecting failure of one node and determining the time of failure, and assigning a failover node based in part on the determined time of failure. This method may also include the steps of determining a time period during which nodes in the cluster are heavily utilized, and assigning a failover node that is not heavily utilized during that time period.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: November 21, 2006
    Assignee: Dell Products L.P.
    Inventors: Victor Mashayekhi, Jenwei Hsieh, Mohamad Reza Rooholamini
  • Patent number: 7137028
    Abstract: A method and system provides an increased robustness and protection against the occurrence of soft errors in parallel connect functional redundancy checking processors. This is achieved by predicting in advance the likely occurrence of a soft error and its impact on the resulting instruction flow and using already existing circuit implementations to hide the transient error.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: November 14, 2006
    Assignee: Intel Corporation
    Inventor: Ronald O. Smith
  • Patent number: 7131027
    Abstract: A system and method for linking external storage systems that includes creating a virtual volume mapping at one or more storage systems. Each virtual volume mapping at each storage system associating a virtual storage volume with a physical storage volume and/or one second virtual storage volume at one or more second storage systems. An access request is received at a first storage system specifying a virtual volume. It is determined on which storage system a physical storage volume associated with the specified virtual volume in the access request is located using the virtual volume mapping at the first storage system and/or the virtual volume mapping at one or more second storage systems. Access is provided to the physical storage volume based on which storage system the physical storage volume is located. Useful in Storage Area Networks and many configurations including 1 to 1, dual path, mirrored, and concatenated, etc.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: October 31, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Shoji Kodama, Akira Yamamoto
  • Patent number: 7120822
    Abstract: A computer executable digital video rendering restoration method is disclosed. Through setting a saving interval, data of states during the rendering process of digital videos are recorded periodically. When the rendering process is abnormally interrupted, the state data in the record file can be immediately used to restore the digital video before the last recording so that the user can continue the digital video rendering.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: October 10, 2006
    Assignee: Cyberlink Corp.
    Inventor: Brian Lin
  • Patent number: 7120831
    Abstract: In an in-circuit emulator system, an in-circuit emulator debugger operated on a personal computer requests operation clock frequency, and transmits data for clock frequency designated by a user to an in-circuit emulator. The in-circuit emulator stores the received clock frequency data in a frequency data register. A PLL synthesizer oscillates with frequency based on the clock frequency data stored in the frequency data register to generate a clock.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: October 10, 2006
    Assignees: Renesas Technology Corp., Mitsubishi Electric Semiconductor Application Engineering Corporation
    Inventor: Chikao Uchino
  • Patent number: 7111190
    Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
  • Patent number: 7111192
    Abstract: The present invention allows a back-up site used for disaster recovery to be constructed in a shorter period of time. In a disk array device 1 at a main site, a copy 4 of a RAID group 3 is generated. In-frame mirroring is used to generate this copy. The RAID group 4 is removed from the disk array device 1 by an operator and transported to a back-up site. The operator then installs each of the disks of the RAID group 4, respectively, in the disk array device 2, in such a manner that they adopt the same positions as in the RAID group 3. The configuration information 5 used in order to manage the RAID group 3 is downloaded to the disk array device 2 in the back-up site, by means of a portable storage medium 8, or via a communications network 7. Thereupon, the differential data between the disk array devices 1, 2 is reflected in the disk array device 2, whereupon construction of the back-up site is complete.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: September 19, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Hiroaki Iguchi
  • Patent number: 7107494
    Abstract: A processing system comprising: i) processor core; ii) a memory; iii) N peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the N peripheral devices that transfers bus request packets between the processor core, the memory, and the N peripheral devices. The communication bus comprises debug circuitry for capturing bus transaction data associated with a bus transaction between a first of the peripheral devices and a second of the peripheral devices and transferring the captured bus transaction data to an external test device.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: September 12, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Brett A. Tischler
  • Patent number: 7096392
    Abstract: A data management system or “DMS” provides an automated, continuous, real-time, substantially no downtime data protection service to one or more data sources associated with a set of application host servers. To facilitate the data protection service, a host driver embedded in an application server captures real-time data transactions, preferably in the form of an event journal that is provided to other DMS components. The driver functions to translate traditional file/database/block I/O and the like into a continuous, application-aware, output data stream. The host driver includes an event processor that provides the data protection service, preferably by implementing a finite state machine (FSM). In particular, the data protection is provided to a given data source in the host server by taking advantage of the continuous, real-time data that the host driver is capturing and providing to other DMS components.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: August 22, 2006
    Assignee: Asempra Technologies, Inc.
    Inventor: Siew Yong Sim-Tang