Abstract: A method, computer system, and apparatus perform a modified simple boot. Rather than following Ver. 1 of the Simple Boot Flag Specification, the simple boot flag is ignored if certain platform corruption errors are detected by the BIOS. When the simple boot flag is set, the BIOS runs through a set of core diagnostics to determine whether a platform corruption has occurred. If BIOS detects that the simple boot flag is set and that no platform corruptions have occurred, then a simple boot is performed. However, if a platform corruption is detected, the set simple boot flag is ignored and a full suite of diagnostics routines is performed by the BIOS during the boot process.

Abstract: The processing of tasks in a processor platform is carried out by distributing the processing procedure over a logical chain of a number of processors in the processor platform. If one of the processors fails, the data is lost and the whole chain remains blocked for a relatively long time. The invention provides a remedy for this by forming a further chain in which significant data relating to state is transferred to the subsequent processor. When restarted, the failed processor can then load this data again and thereby assume a state as before the failure.

Abstract: A fault tolerant network server is described. This server has a pair of processing units, each processing unit has at least one CPU, system memory, an interface for a RAID system, at least one disk drive, a network interface, a cluster network interface, a power supply, and a case. The cases of both processing units are slideably mounted in a rack-mountable server case. The server also has a RAID system mounted in the server case and powered by two, redundant, power supplies and coupled to the processing units through isolators for blocking transactions when a processing unit has insufficient power or is being serviced.

Abstract: A system and method for diagnosing and validating a machine over a network using waveform data. Historical waveform data are obtained via the network from machines having known faults along with corresponding actions for repairing the machines and are used to develop fault classification rules. The fault classification rules are stored in a diagnostic knowledge database. The database of classification rules are used to diagnose new waveform data from a machine having an unknown fault, via the network.

Abstract: A recovery logging method wherein when a node in a computer network becomes unavailable, file systems which require verification and are locked are logged in a recovery log and checking of other file systems continues. In this manner, the host node effectively utilizes time which would otherwise be spent waiting for a file system to become available. Upon completing available file system verifications, those file systems which were logged are checked for availability via background processing. When a logged file system becomes available, it is then verified. During the time spent waiting for a logged file system to become available, the affected node is available for other processing.

Abstract: This specification discloses a method and device for computer testing, which method can perform automatic testing for a plurality of computer on the product line. By describing, recording, and summarizing contents and results of each test item using a script, the defects such as lower efficiency, more errors and longer testing time occurred in human operations can be conquered. The method comprises the steps of: building a structured query language (SQL) server; forming electrical communication between the SQL server and a plurality of computers to be tested; retrieving a command macro from the SQL server according to the-command request sent out from the computer to be tested; controlling the computer to be tested to execute corresponding test commands according to the content of the command macro; receiving and analyzing the execution result of the test command; and displaying the testing result.

Abstract: A logic unit operable under the Byzantine algorithm for the architectural configuration of a composite assembly which tolerates an amount of F errors in simultaneous manner as to time and a plurality of inputs for in-reading of data into registers of a set of registers, and a plurality of outputs for out-reading of data from the registers, whereby each output is connectable with an input of a further logic unit, whereby the registers are coupled with the inputs and outputs in such a manner that each register is capable of being read-in and being capable of being read-out independently of the position of the logic unit within the assembly, by means of a position invariant, relative identification, as well as a computer unit with such a logic unit, as well as the fault-tolerant assembly of such logic/computer units, and a method of operating a fault tolerant assembly.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: A data processing system has at least one integrated circuit containing a central processing unit (CPU) that includes at least first and second processing cores. The integrated circuit also includes input facilities that receive control input specifying which of the processing cores is to be utilized. In addition, the integrated circuit includes configuration logic that decodes the control input and, in response, selectively controls reception of input signals and transmission of output signals of one or more of the processing cores in accordance with the control input. In an illustrative embodiment, the configuration logic is partial-good logic that configures the integrated circuit to utilize the second processing core, in lieu of a defective or inactive first processing core, as a virtual first processing core.