Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract: A high pass filter is disposed to an output part of a gain control amplifier. A gain control signal change detector detects a change of a gain control signal from the gain control amplifier. Upon detection of a change of the gain control signal, a counter and a clock generator generate a cancel pulse which has a certain width, and using the cancel pulse, a first switch cuts an AC signal which is fed to the gain control amplifier. Further, using the same cancel pulse, a second switch reduces the time constant of the high pass filter. Through this operation, a transient response of a DC offset is eliminated.

Abstract: Current source for generating a constant reference current having an amplifier circuit, which outputs a negative feedback voltage, present across a first resistor, in inverted amplified fashion as amplification output voltage; a first voltage/current converter, which generates a current in a manner dependent on the amplifier output voltage; a first current mirror circuit, which mirrors the current generated by the voltage/current converter to form a mirrored current which flows through the first resistor in order to generate the negative feedback voltage; and having a second current mirror circuit, which mirrors the current generated by the voltage/current converter to form the reference current.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is further included which detects a state of the reference voltage (output from a filter circuit) and controls a change of a multiple rate of a divider according to a state of the detected reference voltage. The multiple rate control circuit further outputs control signal LPFOUT for changing a multiple rate so that the PLL clock signal generation circuit does not deviate from a region capable of locking when being detected of deviation from the region capable of locking by detecting the state of reference voltage.

Abstract: A delay line unit of a delay locked loop (DLL) circuit, includes a first delay line having a plurality of first unit delays, each first unit delay having a first delay; a second delay line having a plurality of second unit delays, each second unit delay having a second delay; and a third delay line having a plurality of third unit delays, each third unit delay having a third delay, wherein the first delay is shorter than the second delay, and the second delay is shorter than the third delay.

Abstract: In a conventional semiconductor integrated circuit device, a means for preventing a backflow current has a high on-state resistance, which makes it impossible to reduce the voltage loss in normal operation. A semiconductor integrated circuit device of the invention has a first MOS transistor, a second MOS transistor provided between the first MOS transistor and a power supply terminal, and a means that, in normal operation, keeps the gate of the second MOS transistor at a predetermined potential (preferably the ground potential) and that, when a backflow current is likely, turns the second MOS transistor off. This helps prevent a backflow current while reducing the voltage loss in normal operation.

Abstract: A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (?), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.

Abstract: A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.

Abstract: A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has reached such an extent that large voltage swings in the regeneration circuit are transmitted back to the signal source and corrupt the signal source or neighboring circuits. Furthermore, as controlled by a control circuit, the instant of isolating the signal source can be dependent on the degree of regeneration such as being dependent on a predetermined degree of regeneration. The comparator may be incorporated in an electronic device such as an analog-to-digital converter or a wireless receiver or transceiver.

Abstract: A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.

Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: A pulse-width modulation circuit converts an input signal into a pulse signal to be supplied to a switch amplifying circuit. The modulation circuit includes a comparison signal generator, an amplitude controller for modulating a comparison signal from the signal generator, and a comparator for comparing the modulated comparison signal and the input signal. The comparator outputs a signal whose level is inverted in accordance with the level of the input signal. The signal outputted from the comparator is supplied to the switch amplifying circuit.

Abstract: A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting unit. The reset unit outputs reset signals according to the first and second input signals so as to reset the phase error detecting unit without delay time. Thus, it is possible to make the output timing of the phase error signal in a more precisely linear proportion to the phase error value and to enhance the sensitivity of the phase locked loop.

Abstract: An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.

Abstract: A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode.

Abstract: A high side switching circuit, comprising: a switching transistor; a charge pump drive circuit including a circuit for generating an oscillating signal; and a charge pump arranged to provide a gate drive voltage to the switching transistor in response to a control signal; wherein the charge pump is driven by the charge pump drive circuit, and the circuit for generating an oscillating signal comprises: an oscillator having a power supply input and first and second outputs, outputting first and second pulse trains respectively of the same frequency but out of phase such that when the first pulse train is high, the second pulse train is low and when the second pulse train is high, the first pulse train is low; first and second transistors connected in series with the drain of the first transistor connected to a high voltage input relative to the high level of the first and second pulse train pulses, the source of the first transistor connected to the drain of the second transistor, the source of the second trans

Abstract: A thermal shutdown circuit board integrated circuit device. The thermal shutdown circuit includes a current source for receiving a current bias and generating an output current in accordance therewith. The current source is configured to produce the output current in a manner proportional to absolute temperature. A current mirror is coupled to the current source. The current mirror is configured to mirror the output current from the current source and is configured to have a high output impedance. A thermal shutdown transistor is coupled to control one output of the current mirror. The thermal shutdown transistor is also coupled to receive the output current and shutdown the output current at a temperature threshold in a manner dependent on shutdown circuit operating temperature.

Abstract: A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a voltage supply line. When the delay locked loop is configured to operate in response to an input clock signal having a relatively high frequency, the voltage supply line is coupled to receive a first supply voltage. When the delay locked loop is configured to operate in response to an input clock signal having a relatively low frequency, the voltage supply line is coupled to receive a second supply voltage, which is significantly lower than the first supply voltage. When operating in response to the first supply voltage, the delay elements exhibit relatively short delays. Conversely, when operating in response to the second supply voltage, the delay elements exhibit relatively long delays.

Abstract: An MN counter with analog interpolation (“MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.