Abstract: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Abstract: Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to store electrical characteristics of the delay line circuitry during testing to enable self-calibration of the delay line circuitry.

Abstract: An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Abstract: Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

Abstract: A delay circuit is constructed by connecting taps TAP0–n for providing with a unit delay time (?) in series on multiple stages. Each tap has the same configuration and an objective signal is inputted to a signal input terminal IN1. The output terminal of a preceding stage tap is connected to a between-stages connecting terminal IN2. An output terminal O is connected to the between-stages connecting terminal of a next stage tap. The signal input terminal and the between-stages connecting terminal are connected to one input terminal of NAND gates 1, 2 and a tap selection signal is inputted to the other input terminal. The output terminal is connected to a NAND gate 3. One of the NAND gates 1, 2 functions as a logical inversion gate corresponding to a tap selection signal so as to enable propagation of the signal. At this time, in the other NAND gate, the output signal is fixed to high level and the NAND gate 3 also functions as a logical inversion gate.

Abstract: Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.

Abstract: Certain exemplary embodiments comprise a system, comprising: an electrical isolator adapted to couple a processor of a programmable logic controller to a user load; a transistor adapted to provide switching of a control signal provided by the processor for the user load; a totem pole output coupling the electrical isolator and the transistor and adapted to switch a gate of the transistor; and a power supply adapted to provide a floating regulated DC voltage to the gate of the transistor.

Abstract: Delays induced to leading and trailing edges of an input pulse train are updated faster than before. First and second delay paths receive delay data for inducing delays to leading edges and/or trailing edges of an input pulse train. An OR circuit combines the outputs of the delay paths. First and second gates receive the input pulse train and selectively provide the input pulse train to the first and second delay paths independent of the edge position of the input pulse train. A delay time setup circuit generates a CTRL signal for controlling the first and second gates and the loading of the delay data to the first and second delay path. The CTRL signal causes the gates to selectively switch the input pulse train from one delay path to another while the delay data is selectively loaded in the delay path not receiving the input pulse train.

Abstract: A current supply circuit includes an input, a load terminal, a selectively activatable current regulator, a selectively activatable adjustable current source, and a comparator circuit. The input is configured to receive a first value signal. The load terminal is configured to provide a load current that is dependent on the first value signal. The current regulator is operable to, when activated, cause a first current to be provided through the load based on the first value signal. The adjustable current source is operable to, when activated, cause a second current to be provided through the load based on the first value signal. The comparator circuit is operable to generate a comparison of the first value signal and a second value signal, and is further operable to cause selective activation of one of the current regulator or the adjustable current source based on the comparison.

Abstract: A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitude to a reference signal. The comparator then generates a tail current control signal for the DLL based on a result of the comparison. In one embodiment, the reference signal is indicative of a predetermined tail current value for the DLL, and the tail current control signal adjusts delay of the DLL to equal the predetermined tail current value. Preferably, the tail current control signal maintains the DLL signal output at a substantially constant amplitude in spite of frequency variations and may also be used to set the voltage swing for the DLL.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: As the chip manufacturing process progresses towards making smaller and finer chip circuitry, leakage currents of different types including the subthreshold leakage current, gate tunneling leakage current and GIDL (Gate-Induced Drain Leakage) current increase. These leakage currents increase the electrical current consumption of the chip. In a semiconductor integrated circuit device comprising a circuit block having a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied.

Abstract: A signal generator circuit prevents a shift of a timing at which an output signal at high voltage level changes from a timing at which an output signal at low voltage level changes, and a level shifter prevents a through current from flowing between a high voltage power supply and a ground potential. The signal generator circuit has an output adjustor circuit for outputting a first output signal and a second output signal in accordance with an input signal, and a level shifter for converting a voltage level in accordance with the input signal to generate a third output signal and a fourth output signal. In response to a rising of the input signal, the first output signal first changes, then the third and fourth output signals change, and subsequently the first output signal changes.

Abstract: A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.

Abstract: A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first signal and having a first output signal, and a second bistable element clocked by the second signal and having a second output signal; means for determining the variation of the signal indicative of the phase difference, responsive to the first and second output signals, and a reset circuit having a first and a second inputs respectively connected to the first and second output signals and adapted to determine the resetting of the first and second bistable elements in response to the attainment of a respective prescribed state by the first and the second output signals. The first and second inputs of the reset circuit are substantially symmetrical to each other from the point of view of an input impedance associated to each of them.

Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.

Abstract: A delay locked loop (DLL) capable of correcting a duty ratio including: a clock buffer for receiving an external clock signal and an inverted external clock signal to generate a rising edge clock signal; a delay unit for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction unit for receiving the first and the second internal clock signals and the first and the second delay locking signals to generate a mixed clock signal; a delay model unit for delaying the mixed clock signal to generate a feed-backed clock signal; and a first phase detector for receiving the external clock signal and the feed-backed clock signal to generate the first comparison signal.

Abstract: A system includes an output terminal at which power is provided to a load, wherein the load defines a load current. A respective power supply can be coupled to each of a plurality of input terminals for providing current to the load. Each of a plurality of gate modulated diodes is connected between the output terminal and a respective input terminal. Each gate modulated diode has a forward voltage drop that is controllable by a voltage signal applied to a gate of the gate modulated diode. Control circuitry is operable to apply the voltage signal at the gate of each gate modulated diode to control the respective forward voltage drop so that each power supply provides a substantially equal amount of current to the load.

Abstract: A variable loop bandwidth phase locked loop in which, upon input of a succession of signals “1”, no modulated signal degradation occurs and even at a high symbol rate, the reference signal frequency remains low and the sampling frequencies of a phase-frequency detector and a sigma delta circuit remain low. The phase locked loop comprises: a first modulator which transforms baseband signal TX_DATA into an integer signal for specifying a division number and sends it to a control terminal of a programmable divider; a second modulator which shapes an incoming baseband signal into a prescribed signal waveform and sends it to a voltage controlled oscillator; and a variable current charge pump which changes the loop bandwidth of the phase locked loop according to control signal CUR.