Patents Examined by Titus Wong
  • Patent number: 11119960
    Abstract: Examples disclosed herein involve a first connector that facilitates access to a system, a second connector that facilitates access to the same system, and an adapter controller to facilitate concatenating functionality of the first connector and the second connector when the apparatus is communicatively coupled to the system via the first connector and the second connector; and establish a high speed connection between the system and the apparatus via the first connector and the second connector.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: September 14, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andrew David Bodley, Byron A. Alcorn, Shane Ward
  • Patent number: 11113225
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • Patent number: 11106577
    Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale
  • Patent number: 11108852
    Abstract: A system comprises control circuitry that is operable to assign a first of a plurality of computing devices to serve file system requests destined for any of a first plurality of network addresses; assign a second of the computing devices to serve file system requests destined for any of a second plurality of network addresses; maintain statistics regarding file system requests sent to each of the first plurality of network addresses and the second plurality of network addresses; and reassign, based on the statistics, the first of the computing devices to serve file system requests destined for a selected one of the second plurality of network addresses.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 31, 2021
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel
  • Patent number: 11093422
    Abstract: A processor/endpoint communication coupling configuration system includes a plurality of processing subsystems coupled to a multi-endpoint adapter device by a plurality of communication couplings included on at least one hardware subsystem. A communication coupling configuration engine identifies each at least one hardware subsystem, determines at least one communication coupling configuration capability of the plurality of communication couplings, and determines at least one first multi-endpoint adapter device capability of the multi-endpoint adapter device.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Hendrich M. Hernandez, Yogesh Varma, Kurtis John Bowman, Shyamkumar T. Iyer, John Christopher Beckett
  • Patent number: 11088876
    Abstract: A configurable serial link interface circuit is disclosed. The configurable serial link interface includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. the first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 10, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Ramin Farjadrad
  • Patent number: 11086802
    Abstract: A technique is provided for routing access requests within an interconnect. An apparatus provides a plurality of requester elements for issuing access requests, and a slave element to be accessed in response to the access requests. An interconnect is used to couple the plurality of requester elements with the slave element, and provides an intermediate element that acts as a point of serialisation to order the access requests issued by the plurality of requester elements via the intermediate element. Communication channels are provided within the interconnect to support communication between each of the requester elements and the intermediate element, and between the intermediate element and the slave element.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 10, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Tushar P. Ringe, Mark David Werkheiser, Gurunath Ramagiri
  • Patent number: 11061849
    Abstract: A system for data communications, comprising an upstream component configured to select an in-band peripheral component interconnect express (PCIe) equalization procedure or an out-of-band PCIe equalization procedure and a downstream component configured to respond to the selected one of the in-band PCIe equalization procedure or the out-of-band PCIe equalization procedure to enable PCIe communications with the upstream component.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 13, 2021
    Assignee: DELL PRODUCTS L.P.
    Inventors: Chambers Yin, Jason Pritchard, Andy Qiang Liu, James E. Roche, Lynn Lingyu Kong, Jeremy Qiu
  • Patent number: 11061836
    Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam
  • Patent number: 11055254
    Abstract: A mixed-media Ethernet switch (the “switch”) is configured to allow a variety of devices to communicate on a given network. The switch includes a plurality of ports. Each of the plurality of ports are configured to connect with, and communicate with, a corresponding traditional medium or non-traditional medium.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: July 6, 2021
    Assignee: The Aerospace Corporation
    Inventor: Alexander Clifton Utter
  • Patent number: 11016916
    Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Xiuting C. Man, Jeremy J. Shrall, Deepak Ganapathy, Dorit Shapira
  • Patent number: 11010293
    Abstract: Implementations described herein provide apparatus and methods for storing data in, and retrieving data from, an asynchronous FIFO. Data is received at a write side receiving circuitry residing in a write-side clock domain of the FIFO and stored at a memory location in a data storage buffer having a plurality of locations. Each memory location in the data storage buffer has a binary pointer value corresponding to the respective location. The binary pointer value is converted to a corresponding Gray code symbol and transferred to the read side of the FIFO. At the read side the Gray code symbol is converted back to the corresponding binary pointer value. Read-side control circuitry, using the binary pointer value, transfers the data from the data storage buffer to a data output register residing in a read-side clock domain of the FIFO.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 18, 2021
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Gregory Kovishaner
  • Patent number: 10999587
    Abstract: Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may enable multiple users/viewers to collaboratively control such systems and methods. Additionally, some embodiments may enable control by a set of computer input devices (e.g., keyboard and mouse) to switch between multiple computer systems, possibly by following the movement of a computer input device cursor, between virtual displays, as the cursor is controlled by the set of computer input devices.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 4, 2021
    Inventor: Jack Wade
  • Patent number: 10983931
    Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 20, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter
  • Patent number: 10983930
    Abstract: Techniques for providing an efficient NTB-based data transport in a highly available storage system. The techniques include performing an ordered transfer of a source data buffer from a primary storage node to a secondary storage node over a PCIe NTB, writing a “transfer ID value” for the ordered transfer over the NTB to a “received transfer ID register” of the secondary storage node, performing a remote procedure call (RPC) to send, over a side channel, the transfer ID value as a “sent transfer ID value” to the secondary storage node, and processing the RPC call to verify the value contained in the received transfer ID register against the sent transfer ID value. Having performed the verification, the secondary storage node determines a successful or unsuccessful status of the ordered transfer, and sends an RPC reply to acknowledge or inform the primary storage node of the successful or unsuccessful status.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 20, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Leonid Ravich, Eldad Zinger
  • Patent number: 10970241
    Abstract: A converter system for multi-component systems, comprising a multi-component system adjustment module, includes: an input/output unit, an adjustment unit configured to adjust at least one primary component of a primary multi-component system for each of the at least one primary component given as a probability distribution, a certainty evaluation unit configured to evaluate a certainty parameter of the primary multi-component system, and compare the certainty parameter with a certainty threshold, and a prompt selection unit configured to, if the certainty parameter of the primary multi-component system does not meet the certainty threshold, select a further primary component prompt of the plurality of primary component prompts and instructing the multi-component system adjustment module to perform the above steps on the basis of the further primary component prompt; wherein the converter system further comprises a multi-component system converter module, comprising: a converter unit configured to generate a p
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 6, 2021
    Assignee: SAP SE
    Inventor: Giancarlo Frison
  • Patent number: 10956351
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Parthasarathy, Ramamurthy Krithivas, Bradley Burres, Pawel Szymanski, Yi-Feng Liu
  • Patent number: 10949130
    Abstract: A virtual solid state storage system is provided with solid state storage error emulation. An exemplary apparatus comprises a virtual solid state storage device configured to emulate a solid state storage device. The virtual solid state storage device comprises an interface that communicates with a solid state storage controller; an address translation module that translates memory addresses from a solid state storage-based memory space to a second memory space of a second memory device; and a non-solid state storage memory controller that communicates with the second memory device; and an error module to emulate solid state storage errors for testing error handling functions of the solid state storage controller for predefined error types of the solid state storage memory device by: (i) flipping bits sent to and/or read from the second memory device; and/or (ii) changing a status response sent to the solid state storage controller.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 16, 2021
    Assignee: Seagate Technology LLC
    Inventors: Swapnil Rameshrao Khandare, Deepak Govind Choudhary
  • Patent number: 10936480
    Abstract: Intelligent memory brokering for multiple process instances, such as relational databases (e.g., SQL servers), reclaims memory based on value, thereby minimizing cost across instances. An exemplary solution includes: based at least on a trigger event, determining a memory profile for each of a plurality of process instances at a computing node; determining an aggregate memory profile, the aggregate memory profile indicating a memory unit cost for each of a plurality of memory units; determining a count of memory units to be reclaimed; identifying, based at least on the aggregate memory profile and the count of memory units to be reclaimed, a count of memory units to be reclaimed within each process instance so that a total cost is minimized to reclaim the determined count; and communicating, to each process instance having identified memory units to be reclaimed, a count of memory units to be reclaimed within the process instance.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Manoj Syamala, Vivek Narasayya, Junfeng Dong, Ajay Kalhan, Shize Xu, Changsong Li, Pankaj Arora, Jiaqi Liu, John M. Oslake, Arnd Christian König
  • Patent number: 10929322
    Abstract: An arbiter may include a plurality of cells, mapping logic, a fixed priority arbiter, and unmapping logic. Each cell may be associated with a corresponding client and configured to store a priority for the corresponding client. The mapping logic may be connected to the plurality of cells to order requests received from the clients according to the priorities stored in the cells. The fixed priority arbiter may receive the ordered requests and generate a grant for a winning request of the requests. The unmapping logic may use the stored priorities to yield the grant back to the winning client that sent the winning request.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 23, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nicholas George McDonald, Darel Neal Emmot