Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.

Abstract: Systems and methods of writing data acquired from measurement instrumentation. Embodiments include establishing a direct data connection between the test equipment and a network storage drive, generating test data from a sample under test, and writing the test data to the network storage drive without assistance of a computerized controlling device configured to control the testing device.

Abstract: A method for performing a write operation includes selecting, by a host, at least a free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB for tracking the free write buffer; sending, by the host, at least a logical address accessed from the cache structure with respect to the selected write buffer to issue a write-command to a non-volatile memory; receiving a locking instruction of the selected write buffer from the non-volatile memory; updating a status of the selected write buffer within the cache structure based on the received locking instruction; and allowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Abstract: A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.

Abstract: One variation of a system for implementing a key-value data store includes one or more processors, storage media and instructions stored in the storage media which, when executed by the system cause the system to: receive a request store a particular key-value item; request a first networked distributed data storage system to store the particular key-value item; based on a determination that a set of one or more offload criteria is satisfied: retrieve a first set of key-value items from the first networked distributed data storage system, and request a second networked distributed data storage system to store the first set of key-value items in a first set of one or more data objects. The first networked distributed data storage system can have a lower data write latency and a higher data storage cost than the second networked distributed data storage system.

Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

Abstract: A system comprises control circuitry that is operable to assign a first of a plurality of computing devices to serve file system requests destined for any of a first plurality of network addresses; assign a second of the computing devices to serve file system requests destined for any of a second plurality of network addresses; maintain statistics regarding file system requests sent to each of the first plurality of network addresses and the second plurality of network addresses; and reassign, based on the statistics, the first of the computing devices to serve file system requests destined for a selected one of the second plurality of network addresses.

Abstract: A method for operating a data bus subscriber of a local bus, particularly of a ring bus, the method including the steps of: receiving a first data packet over the local bus, wherein the first data packet has an address of the data bus subscriber to which it is directed and at least one instructions list, having a set of instructions for processing process data, receiving a second data packet over the local bus, wherein the second data packet has process data; and executing instructions of the at least one instructions list for processing the received process data. A corresponding data bus subscriber and a local bus master is also provided.

Abstract: Intelligent memory brokering for multiple process instances, such as relational databases (e.g., SQL servers), reclaims memory based on value, thereby minimizing cost across instances. An exemplary solution includes: based at least on a trigger event, determining a memory profile for each of a plurality of process instances at a computing node; determining an aggregate memory profile, the aggregate memory profile indicating a memory unit cost for each of a plurality of memory units; determining a count of memory units to be reclaimed; identifying, based at least on the aggregate memory profile and the count of memory units to be reclaimed, a count of memory units to be reclaimed within each process instance so that a total cost is minimized to reclaim the determined count; and communicating, to each process instance having identified memory units to be reclaimed, a count of memory units to be reclaimed within the process instance.

Abstract: Systems and methods for implementing accelerated memory transfers in an integrated circuit includes configuring a region of memory of an on-chip data buffer based on a neural network computation graph, wherein configuring the region of memory includes: partitioning the region of memory of the on-chip data buffer to include a first distinct sub-region of memory and a second distinct sub-region of memory; initializing a plurality of distinct memory transfer operations from the off-chip main memory to the on-chip data buffer; executing a first set of memory transfer operations that includes writing a first set of computational components to the first distinct sub-region of memory, and while executing, using the integrated circuit, a leading computation based on the first set of computational components, executing a second set of memory transfer operations to the second distinct sub-region of memory for an impending computation.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

Abstract: A device for contactless communication with a terminal, comprising: an antenna for communication with the terminal; an embedded chip configured to communicate with the terminal in accordance with a contactless transmission protocol whereby a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip to maintain a connection with the terminal, the embedded chip being configured to communicate requests to the terminal to extend the waiting time for response; and a module configured to perform processing formed of a plurality of discrete operations, the module being configured to, in response to completing a subset of one or more discrete operations within a waiting time interval set by the terminal, send a first type of command to the embedded chip if the processing is not complete; wherein the embedded chip is further configured to, in response to receiving the first type of command, communicate a request to the terminal to extend the waiting time for response.

Abstract: Methods for operating a memory device can include monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification. The notification can be an added functionality incorporated into a standardized interface.

Abstract: A communication gateway for communicating data frames for a motor vehicle, the gateway being intended to be connected to a plurality of electronic control units in order to exchange data frames, the gateway including: as many management modules as there are electronic control units; a memory in which are stored a lookup table including an index list, with each of the indices of which is associated a memory space, a level-zero addressing table, a level-one addressing table, a level-two addressing table and an address table of levels; a space manager for managing spaces of the lookup table that is configured to determine a free index in the lookup table, and when a memory space of the lookup table is freed or is filled, to modify the byte stored in each memory region of each addressing table associated with the index.

Abstract: Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Abstract: Video editing software tools platform utilizing a video display to provide access to specific video editing software tools, such as video oriented applications or widgets, that can assist those in a video broadcasting team, such as a camera operator or video editor, with a video broadcast feed. Various video editing software tools can provide features and functions that can add visual context to video data presented in the image stream from the video camera and provide archived information pertaining to the same. Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may enable multiple users/viewers to collaboratively control such systems and methods.

Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.